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Extend verilator main loop to support clock generation in C++ #2108

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marlonjames opened this issue Oct 8, 2020 · 0 comments · May be fixed by #2275
Open

Extend verilator main loop to support clock generation in C++ #2108

marlonjames opened this issue Oct 8, 2020 · 0 comments · May be fixed by #2275
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category:performance performance topics category:simulators:verilator Verilator type:feature new or enhanced functionality

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@marlonjames
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Support a user-defined callback in the Pre-Active region of the time step.

This would allow users to create low-level clocks and avoid the VPI->Python overhead, thus improving simulation speed.

Something like below (this assumes #2105 main_time change):

vluint64_t next_usercb_time = 0;

...

// Initial user callback at time 0
next_usercb_time = user_cb(top);

...

while (!Verilated::gotFinish())  {

    ...

    main_time = VerilatedVpi::cbNextDeadline();

    // Don't skip past the next user callback time
    if (next_usercb_time < main_time) {
        main_time = next_usercb_time;
    }

    VerilatedVpi::callCbs(cbNextSimTime);

    // Call user callback for clock toggle
    // Save next time to call it
    if (main_time == next_usercb_time) {
        next_usercb_time = user_cb(top);
    }

    VerilatedVpi::callTimedCbs();
}
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Labels
category:performance performance topics category:simulators:verilator Verilator type:feature new or enhanced functionality
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