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microkernels.cmake
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microkernels.cmake
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# Copyright 2022 Google LLC
#
# This source code is licensed under the BSD-style license found in the
# LICENSE file in the root directory of this source tree.
#
# Description: microkernel filename lists.
#
# Auto-generated file. Do not edit!
# Generator: tools/update-microkernels.py
SET(ALL_ARMSIMD32_MICROKERNEL_SRCS
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x1c4-minmax-fp32-armsimd32.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x2c4-minmax-fp32-armsimd32.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x1c4-minmax-fp32-armsimd32.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x2c4-minmax-fp32-armsimd32.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x1c4-minmax-fp32-armsimd32.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x2c4-minmax-fp32-armsimd32.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x1c4-minmax-fp32-armsimd32.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x2c4-minmax-fp32-armsimd32.c
src/qs8-vcvt/gen/qs8-vcvt-armsimd32-u4.c
src/qs8-vcvt/gen/qs8-vcvt-armsimd32-u8.c
src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-u4.c
src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-u8.c
src/qu8-gemm/gen/qu8-gemm-1x1c4-minmax-fp32-armsimd32.c
src/qu8-gemm/gen/qu8-gemm-1x2c4-minmax-fp32-armsimd32.c
src/qu8-gemm/gen/qu8-gemm-2x1c4-minmax-fp32-armsimd32.c
src/qu8-gemm/gen/qu8-gemm-2x2c4-minmax-fp32-armsimd32.c
src/qu8-igemm/gen/qu8-igemm-1x1c4-minmax-fp32-armsimd32.c
src/qu8-igemm/gen/qu8-igemm-1x2c4-minmax-fp32-armsimd32.c
src/qu8-igemm/gen/qu8-igemm-2x1c4-minmax-fp32-armsimd32.c
src/qu8-igemm/gen/qu8-igemm-2x2c4-minmax-fp32-armsimd32.c
src/qu8-vcvt/gen/qu8-vcvt-armsimd32-u4.c
src/qu8-vcvt/gen/qu8-vcvt-armsimd32-u8.c
src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-u4.c
src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-u8.c)
SET(ALL_AVX_MICROKERNEL_SRCS
src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u8.c
src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u16.c
src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u24.c
src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u32.c
src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u8.c
src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u16.c
src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u24.c
src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u32.c
src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-6f6m7l8c8s4r-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-6f6m7l8c8s4r-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-6f6m7l16c8s4r-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-6f6m7l16c8s4r-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-8f8m9l8c8s4r-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-8f8m9l8c8s4r-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-8f8m9l16c8s4r-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-8f8m9l16c8s4r-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-avx.c
src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx-acc2.c
src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx.c
src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u8.c
src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u16.c
src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u24.c
src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u32.c
src/f32-gemm/gen/f32-gemm-1x8-minmax-avx-broadcast.c
src/f32-gemm/gen/f32-gemm-1x16-minmax-avx-broadcast.c
src/f32-gemm/gen/f32-gemm-3x16-minmax-avx-broadcast.c
src/f32-gemm/gen/f32-gemm-4x8-minmax-avx-broadcast.c
src/f32-gemm/gen/f32-gemm-4x16-minmax-avx-broadcast.c
src/f32-gemm/gen/f32-gemm-5x8-minmax-avx-broadcast.c
src/f32-gemm/gen/f32-gemm-5x16-minmax-avx-broadcast.c
src/f32-gemm/gen/f32-gemm-6x8-minmax-avx-broadcast.c
src/f32-gemm/gen/f32-gemm-6x16-minmax-avx-broadcast.c
src/f32-gemm/gen/f32-gemm-7x8-minmax-avx-broadcast.c
src/f32-gemminc/gen/f32-gemminc-1x8-minmax-avx-broadcast.c
src/f32-gemminc/gen/f32-gemminc-1x16-minmax-avx-broadcast.c
src/f32-gemminc/gen/f32-gemminc-3x16-minmax-avx-broadcast.c
src/f32-gemminc/gen/f32-gemminc-4x8-minmax-avx-broadcast.c
src/f32-gemminc/gen/f32-gemminc-4x16-minmax-avx-broadcast.c
src/f32-gemminc/gen/f32-gemminc-5x8-minmax-avx-broadcast.c
src/f32-gemminc/gen/f32-gemminc-5x16-minmax-avx-broadcast.c
src/f32-gemminc/gen/f32-gemminc-6x8-minmax-avx-broadcast.c
src/f32-gemminc/gen/f32-gemminc-6x16-minmax-avx-broadcast.c
src/f32-gemminc/gen/f32-gemminc-7x8-minmax-avx-broadcast.c
src/f32-igemm/gen/f32-igemm-1x8-minmax-avx-broadcast.c
src/f32-igemm/gen/f32-igemm-1x16-minmax-avx-broadcast.c
src/f32-igemm/gen/f32-igemm-3x16-minmax-avx-broadcast.c
src/f32-igemm/gen/f32-igemm-4x8-minmax-avx-broadcast.c
src/f32-igemm/gen/f32-igemm-4x16-minmax-avx-broadcast.c
src/f32-igemm/gen/f32-igemm-5x8-minmax-avx-broadcast.c
src/f32-igemm/gen/f32-igemm-5x16-minmax-avx-broadcast.c
src/f32-igemm/gen/f32-igemm-6x8-minmax-avx-broadcast.c
src/f32-igemm/gen/f32-igemm-6x16-minmax-avx-broadcast.c
src/f32-igemm/gen/f32-igemm-7x8-minmax-avx-broadcast.c
src/f32-prelu/gen/f32-prelu-avx-2x8.c
src/f32-prelu/gen/f32-prelu-avx-2x16.c
src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x16-minmax-avx-broadcast.c
src/f32-qc4w-gemm/gen/f32-qc4w-gemm-2x16-minmax-avx-broadcast.c
src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x16-minmax-avx-broadcast.c
src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x16-minmax-avx-broadcast.c
src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x16-minmax-avx-broadcast.c
src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x16-minmax-avx-broadcast.c
src/f32-qc4w-gemm/gen/f32-qc4w-gemm-7x16-minmax-avx-broadcast.c
src/f32-qc4w-gemm/gen/f32-qc4w-gemm-8x16-minmax-avx-broadcast.c
src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16-minmax-avx-broadcast.c
src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x16-minmax-avx-broadcast.c
src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x16-minmax-avx-broadcast.c
src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16-minmax-avx-broadcast.c
src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x16-minmax-avx-broadcast.c
src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x16-minmax-avx-broadcast.c
src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x16-minmax-avx-broadcast.c
src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x16-minmax-avx-broadcast.c
src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u8.c
src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u16.c
src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u24.c
src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u32.c
src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u8.c
src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u16.c
src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u24.c
src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u32.c
src/f32-rdsum/gen/f32-rdsum-7p7x-minmax-avx-c16.c
src/f32-rdsum/gen/f32-rdsum-7p7x-minmax-avx-c32.c
src/f32-rdsum/gen/f32-rdsum-7p7x-minmax-avx-c64.c
src/f32-rminmax/gen/f32-rmax-avx-u8.c
src/f32-rminmax/gen/f32-rmax-avx-u16-acc2.c
src/f32-rminmax/gen/f32-rmax-avx-u24-acc3.c
src/f32-rminmax/gen/f32-rmax-avx-u32-acc2.c
src/f32-rminmax/gen/f32-rmax-avx-u32-acc4.c
src/f32-rminmax/gen/f32-rmin-avx-u8.c
src/f32-rminmax/gen/f32-rmin-avx-u16-acc2.c
src/f32-rminmax/gen/f32-rmin-avx-u24-acc3.c
src/f32-rminmax/gen/f32-rmin-avx-u32-acc2.c
src/f32-rminmax/gen/f32-rmin-avx-u32-acc4.c
src/f32-rminmax/gen/f32-rminmax-avx-u8.c
src/f32-rminmax/gen/f32-rminmax-avx-u16-acc2.c
src/f32-rminmax/gen/f32-rminmax-avx-u24-acc3.c
src/f32-rminmax/gen/f32-rminmax-avx-u32-acc2.c
src/f32-rminmax/gen/f32-rminmax-avx-u32-acc4.c
src/f32-rsum/gen/f32-rsum-avx-u8.c
src/f32-rsum/gen/f32-rsum-avx-u16-acc2.c
src/f32-rsum/gen/f32-rsum-avx-u24-acc3.c
src/f32-rsum/gen/f32-rsum-avx-u32-acc2.c
src/f32-rsum/gen/f32-rsum-avx-u32-acc4.c
src/f32-vbinary/gen/f32-vadd-minmax-avx-u8.c
src/f32-vbinary/gen/f32-vadd-minmax-avx-u16.c
src/f32-vbinary/gen/f32-vaddc-minmax-avx-u8.c
src/f32-vbinary/gen/f32-vaddc-minmax-avx-u16.c
src/f32-vbinary/gen/f32-vdiv-minmax-avx-u8.c
src/f32-vbinary/gen/f32-vdiv-minmax-avx-u16.c
src/f32-vbinary/gen/f32-vdivc-minmax-avx-u8.c
src/f32-vbinary/gen/f32-vdivc-minmax-avx-u16.c
src/f32-vbinary/gen/f32-vmax-avx-u8.c
src/f32-vbinary/gen/f32-vmax-avx-u16.c
src/f32-vbinary/gen/f32-vmaxc-avx-u8.c
src/f32-vbinary/gen/f32-vmaxc-avx-u16.c
src/f32-vbinary/gen/f32-vmin-avx-u8.c
src/f32-vbinary/gen/f32-vmin-avx-u16.c
src/f32-vbinary/gen/f32-vminc-avx-u8.c
src/f32-vbinary/gen/f32-vminc-avx-u16.c
src/f32-vbinary/gen/f32-vmul-minmax-avx-u8.c
src/f32-vbinary/gen/f32-vmul-minmax-avx-u16.c
src/f32-vbinary/gen/f32-vmulc-minmax-avx-u8.c
src/f32-vbinary/gen/f32-vmulc-minmax-avx-u16.c
src/f32-vbinary/gen/f32-vrdivc-minmax-avx-u8.c
src/f32-vbinary/gen/f32-vrdivc-minmax-avx-u16.c
src/f32-vbinary/gen/f32-vrsubc-minmax-avx-u8.c
src/f32-vbinary/gen/f32-vrsubc-minmax-avx-u16.c
src/f32-vbinary/gen/f32-vsqrdiff-avx-u8.c
src/f32-vbinary/gen/f32-vsqrdiff-avx-u16.c
src/f32-vbinary/gen/f32-vsqrdiffc-avx-u8.c
src/f32-vbinary/gen/f32-vsqrdiffc-avx-u16.c
src/f32-vbinary/gen/f32-vsub-minmax-avx-u8.c
src/f32-vbinary/gen/f32-vsub-minmax-avx-u16.c
src/f32-vbinary/gen/f32-vsubc-minmax-avx-u8.c
src/f32-vbinary/gen/f32-vsubc-minmax-avx-u16.c
src/f32-vclamp/gen/f32-vclamp-avx-u8.c
src/f32-vclamp/gen/f32-vclamp-avx-u16.c
src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u8.c
src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u16.c
src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u24.c
src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u32.c
src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u40.c
src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u48.c
src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u8.c
src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u16.c
src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u24.c
src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u32.c
src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u40.c
src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u48.c
src/f32-velu/gen/f32-velu-avx-rr2-p6-u8.c
src/f32-velu/gen/f32-velu-avx-rr2-p6-u16.c
src/f32-velu/gen/f32-velu-avx-rr2-p6-u24.c
src/f32-velu/gen/f32-velu-avx-rr2-p6-u32.c
src/f32-velu/gen/f32-velu-avx-rr2-p6-u40.c
src/f32-velu/gen/f32-velu-avx-rr2-p6-u48.c
src/f32-vhswish/gen/f32-vhswish-avx-u8.c
src/f32-vhswish/gen/f32-vhswish-avx-u16.c
src/f32-vlrelu/gen/f32-vlrelu-avx-u8.c
src/f32-vlrelu/gen/f32-vlrelu-avx-u16.c
src/f32-vrelu/gen/f32-vrelu-avx-u8.c
src/f32-vrelu/gen/f32-vrelu-avx-u16.c
src/f32-vrnd/gen/f32-vrndd-avx-u8.c
src/f32-vrnd/gen/f32-vrndd-avx-u16.c
src/f32-vrnd/gen/f32-vrndne-avx-u8.c
src/f32-vrnd/gen/f32-vrndne-avx-u16.c
src/f32-vrnd/gen/f32-vrndu-avx-u8.c
src/f32-vrnd/gen/f32-vrndu-avx-u16.c
src/f32-vrnd/gen/f32-vrndz-avx-u8.c
src/f32-vrnd/gen/f32-vrndz-avx-u16.c
src/f32-vrsqrt/gen/f32-vrsqrt-avx-rsqrt-u8.c
src/f32-vrsqrt/gen/f32-vrsqrt-avx-rsqrt-u16.c
src/f32-vrsqrt/gen/f32-vrsqrt-avx-rsqrt-u32.c
src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u8.c
src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u16.c
src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u24.c
src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u32.c
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src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u64.c
src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u72.c
src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u80.c
src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u8.c
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src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u24.c
src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u32.c
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src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u72.c
src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u80.c
src/f32-vsqrt/gen/f32-vsqrt-avx-rsqrt-u8.c
src/f32-vsqrt/gen/f32-vsqrt-avx-rsqrt-u16.c
src/f32-vsqrt/gen/f32-vsqrt-avx-rsqrt-u32.c
src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-u8.c
src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-u16.c
src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-u32.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u8.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u16.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u24.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u32.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u40.c
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src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u64.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u72.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u80.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u8.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u16.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u24.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u32.c
src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u8.c
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src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-div-u8.c
src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-div-u16.c
src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-div-u24.c
src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-div-u32.c
src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-nr-u8.c
src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-nr-u16.c
src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-nr-u24.c
src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-nr-u32.c
src/f32-vunary/gen/f32-vabs-avx-u8.c
src/f32-vunary/gen/f32-vabs-avx-u16.c
src/f32-vunary/gen/f32-vneg-avx-u8.c
src/f32-vunary/gen/f32-vneg-avx-u16.c
src/f32-vunary/gen/f32-vsqr-avx-u8.c
src/f32-vunary/gen/f32-vsqr-avx-u16.c
src/math/f32-exp-avx-rr2-p5.c
src/math/f32-expm1minus-avx-rr2-lut4-p4-perm.c
src/math/f32-expm1minus-avx-rr2-lut16-p3.c
src/math/f32-expm1minus-avx-rr2-p6.c
src/math/f32-sigmoid-avx-rr2-lut64-p2-div.c
src/math/f32-sigmoid-avx-rr2-p5-div.c
src/math/f32-sigmoid-avx-rr2-p5-nr1.c
src/math/f32-sigmoid-avx-rr2-p5-nr2.c
src/math/gen/f32-tanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div.c
src/math/gen/f32-tanh-avx-expm1minus-rr1-lut8-p4h3ps-div.c
src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-div.c
src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-nr1.c
src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-nr2.c
src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h2ts-nr1.c
src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h2ts-nr2.c
src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ps-nr1.c
src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ps-nr2.c
src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ts-nr1.c
src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ts-nr2.c
src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4c8-minmax-avx-ld64.c
src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4c8-minmax-avx-ld128.c
src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x4c8-minmax-avx-ld64.c
src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x4c8-minmax-avx-ld128.c
src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x4c8-minmax-avx-ld64.c
src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x4c8-minmax-avx-ld128.c
src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4c8-minmax-avx-ld64.c
src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4c8-minmax-avx-ld128.c
src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-avx-ld64.c
src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-avx-ld128.c
src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-avx-ld64.c
src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-avx-ld128.c
src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-avx-ld64.c
src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-avx-ld128.c
src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-avx-ld64.c
src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-avx-ld128.c
src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-1x4c8-minmax-avx-ld64.c
src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-1x4c8-minmax-avx-ld128.c
src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-2x4c8-minmax-avx-ld64.c
src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-2x4c8-minmax-avx-ld128.c
src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-3x4c8-minmax-avx-ld64.c
src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-3x4c8-minmax-avx-ld128.c
src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-4x4c8-minmax-avx-ld64.c
src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-4x4c8-minmax-avx-ld128.c
src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c
src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c
src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c
src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c
src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c
src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c
src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul16-add16.c
src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul16.c
src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul32.c
src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul16-add16.c
src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul16.c
src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul32.c
src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul16-add16.c
src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul16.c
src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul32.c
src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul16-add16.c
src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul16.c
src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul32.c
src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u8.c
src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u16.c
src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u24.c
src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-avx-mul16-add16.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx-mul16-add16.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx-mul16.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx-mul32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx-mul16-add16.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx-mul16.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx-mul32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx-mul16-add16.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx-mul16.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx-mul32.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx-mul16-add16.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx-mul16.c
src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx-mul32.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-avx-ld128.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-avx-ld128.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-avx-ld128.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-avx-ld128.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-avx-ld128.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-avx-ld128.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-avx-ld128.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-avx-ld128.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-avx-ld128.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-avx-ld128.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-avx-ld64.c
src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-avx-ld128.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-avx-ld64.c
src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-avx-ld128.c
src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u8.c
src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u16.c
src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u24.c
src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u32.c
src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u8.c
src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u16.c
src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u24.c
src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u32.c
src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u8.c
src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u16.c
src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u24.c
src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u32.c
src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u8.c
src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u16.c
src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u24.c
src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u32.c
src/qs8-vcvt/gen/qs8-vcvt-avx-u8.c
src/qs8-vcvt/gen/qs8-vcvt-avx-u16.c
src/qs8-vcvt/gen/qs8-vcvt-avx-u32.c
src/qs8-vhswish/gen/qs8-vhswish-avx-u8.c
src/qs8-vhswish/gen/qs8-vhswish-avx-u16.c
src/qs8-vhswish/gen/qs8-vhswish-avx-u32.c
src/qs8-vlrelu/gen/qs8-vlrelu-avx-u8.c
src/qs8-vlrelu/gen/qs8-vlrelu-avx-u16.c
src/qs8-vlrelu/gen/qs8-vlrelu-avx-u32.c
src/qs8-vmul/gen/qs8-vmul-minmax-fp32-avx-mul16-ld64-u8.c
src/qs8-vmul/gen/qs8-vmul-minmax-fp32-avx-mul16-ld64-u16.c
src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-avx-mul16-ld64-u8.c
src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-avx-mul16-ld64-u16.c
src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-u4.c
src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-u8.c
src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-u16.c
src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c
src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c
src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c
src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c
src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c
src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c
src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx-mul16.c
src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx-mul32.c
src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx-mul16.c
src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx-mul32.c
src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx-mul16.c
src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx-mul32.c
src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx-mul16.c
src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx-mul32.c
src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u8.c
src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u16.c
src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u24.c
src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u32.c
src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-avx-ld128.c
src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-avx-ld128.c
src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-avx-ld128.c
src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-avx-ld128.c
src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-avx-ld128.c
src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-avx-ld128.c
src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-avx-ld128.c
src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-avx-ld128.c
src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-avx-ld128.c
src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-avx-ld128.c
src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-avx-ld64.c
src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-avx-ld128.c
src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-avx-ld64.c
src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-avx-ld128.c
src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul16-ld64-u8.c
src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul16-ld64-u16.c
src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul32-ld32-u8.c
src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul32-ld32-u16.c
src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul16-ld64-u8.c
src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul16-ld64-u16.c
src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul32-ld32-u8.c
src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul32-ld32-u16.c
src/qu8-vcvt/gen/qu8-vcvt-avx-u8.c
src/qu8-vcvt/gen/qu8-vcvt-avx-u16.c
src/qu8-vcvt/gen/qu8-vcvt-avx-u32.c
src/qu8-vhswish/gen/qu8-vhswish-avx-u8.c
src/qu8-vhswish/gen/qu8-vhswish-avx-u16.c
src/qu8-vhswish/gen/qu8-vhswish-avx-u32.c
src/qu8-vlrelu/gen/qu8-vlrelu-avx-u8.c
src/qu8-vlrelu/gen/qu8-vlrelu-avx-u16.c
src/qu8-vlrelu/gen/qu8-vlrelu-avx-u32.c
src/qu8-vmul/gen/qu8-vmul-minmax-fp32-avx-mul16-ld64-u8.c
src/qu8-vmul/gen/qu8-vmul-minmax-fp32-avx-mul16-ld64-u16.c
src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-avx-mul16-ld64-u8.c
src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-avx-mul16-ld64-u16.c
src/x8-lut/gen/x8-lut-avx-u16.c
src/x8-lut/gen/x8-lut-avx-u32.c
src/x8-lut/gen/x8-lut-avx-u48.c
src/x8-lut/gen/x8-lut-avx-u64.c
src/x32-packw/gen/x32-packw-x8-gemm-goi-avx-u4-prfm.c
src/x32-packw/gen/x32-packw-x8-gemm-goi-avx-u4.c
src/x32-packw/gen/x32-packw-x8s4-gemm-goi-avx-u4-prfm.c
src/x32-packw/gen/x32-packw-x8s4-gemm-goi-avx-u4.c
src/x32-packw/gen/x32-packw-x16-gemm-goi-avx-u4-prfm.c
src/x32-packw/gen/x32-packw-x16-gemm-goi-avx-u4.c
src/x32-packw/gen/x32-packw-x16s4-gemm-goi-avx-u4-prfm.c
src/x32-packw/gen/x32-packw-x16s4-gemm-goi-avx-u4.c
src/x32-transposec/gen/x32-transposec-8x8-multi-mov-avx.c
src/x32-transposec/gen/x32-transposec-8x8-multi-switch-avx.c
src/x32-transposec/gen/x32-transposec-8x8-reuse-mov-avx.c
src/x32-transposec/gen/x32-transposec-8x8-reuse-multi-avx.c
src/x32-transposec/gen/x32-transposec-8x8-reuse-switch-avx.c
src/x64-transposec/gen/x64-transposec-4x4-multi-mov-avx.c
src/x64-transposec/gen/x64-transposec-4x4-multi-multi-avx.c
src/x64-transposec/gen/x64-transposec-4x4-multi-switch-avx.c
src/x64-transposec/gen/x64-transposec-4x4-reuse-mov-avx.c
src/x64-transposec/gen/x64-transposec-4x4-reuse-multi-avx.c
src/x64-transposec/gen/x64-transposec-4x4-reuse-switch-avx.c)
SET(ALL_AVX2_MICROKERNEL_SRCS
src/f16-f32acc-gemm/gen/f16-f32acc-gemm-1x8-minmax-avx2-broadcast.c
src/f16-f32acc-gemm/gen/f16-f32acc-gemm-1x16-minmax-avx2-broadcast.c
src/f16-f32acc-gemm/gen/f16-f32acc-gemm-3x16-minmax-avx2-broadcast.c
src/f16-f32acc-gemm/gen/f16-f32acc-gemm-4x8-minmax-avx2-broadcast.c
src/f16-f32acc-gemm/gen/f16-f32acc-gemm-4x16-minmax-avx2-broadcast.c
src/f16-f32acc-gemm/gen/f16-f32acc-gemm-5x8-minmax-avx2-broadcast.c
src/f16-f32acc-gemm/gen/f16-f32acc-gemm-5x16-minmax-avx2-broadcast.c
src/f16-f32acc-gemm/gen/f16-f32acc-gemm-6x8-minmax-avx2-broadcast.c
src/f16-f32acc-gemm/gen/f16-f32acc-gemm-7x8-minmax-avx2-broadcast.c
src/f16-f32acc-igemm/gen/f16-f32acc-igemm-1x8-minmax-avx2-broadcast.c
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src/qd8-f16-qc8w-gemm/gen/qd8-f16-qc8w-gemm-2x8c8-minmax-avx2.c
src/qd8-f16-qc8w-gemm/gen/qd8-f16-qc8w-gemm-3x8c8-minmax-avx2.c
src/qd8-f16-qc8w-gemm/gen/qd8-f16-qc8w-gemm-4x8c8-minmax-avx2.c
src/qd8-f16-qc8w-igemm/gen/qd8-f16-qc8w-igemm-1x8c8-minmax-avx2.c
src/qd8-f16-qc8w-igemm/gen/qd8-f16-qc8w-igemm-2x8c8-minmax-avx2.c
src/qd8-f16-qc8w-igemm/gen/qd8-f16-qc8w-igemm-3x8c8-minmax-avx2.c
src/qd8-f16-qc8w-igemm/gen/qd8-f16-qc8w-igemm-4x8c8-minmax-avx2.c
src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x8c8-minmax-avx2.c