-
Notifications
You must be signed in to change notification settings - Fork 326
/
microkernels.bzl
10036 lines (9985 loc) · 665 KB
/
microkernels.bzl
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
"""
Microkernel filenames lists.
Auto-generated file. Do not edit!
Generator: tools/update-microkernels.py
"""
ALL_ARMSIMD32_MICROKERNEL_SRCS = [
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x1c4-minmax-fp32-armsimd32.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x2c4-minmax-fp32-armsimd32.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x1c4-minmax-fp32-armsimd32.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x2c4-minmax-fp32-armsimd32.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x1c4-minmax-fp32-armsimd32.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x2c4-minmax-fp32-armsimd32.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x1c4-minmax-fp32-armsimd32.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x2c4-minmax-fp32-armsimd32.c",
"src/qs8-vcvt/gen/qs8-vcvt-armsimd32-u4.c",
"src/qs8-vcvt/gen/qs8-vcvt-armsimd32-u8.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-u4.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-u8.c",
"src/qu8-gemm/gen/qu8-gemm-1x1c4-minmax-fp32-armsimd32.c",
"src/qu8-gemm/gen/qu8-gemm-1x2c4-minmax-fp32-armsimd32.c",
"src/qu8-gemm/gen/qu8-gemm-2x1c4-minmax-fp32-armsimd32.c",
"src/qu8-gemm/gen/qu8-gemm-2x2c4-minmax-fp32-armsimd32.c",
"src/qu8-igemm/gen/qu8-igemm-1x1c4-minmax-fp32-armsimd32.c",
"src/qu8-igemm/gen/qu8-igemm-1x2c4-minmax-fp32-armsimd32.c",
"src/qu8-igemm/gen/qu8-igemm-2x1c4-minmax-fp32-armsimd32.c",
"src/qu8-igemm/gen/qu8-igemm-2x2c4-minmax-fp32-armsimd32.c",
"src/qu8-vcvt/gen/qu8-vcvt-armsimd32-u4.c",
"src/qu8-vcvt/gen/qu8-vcvt-armsimd32-u8.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-u4.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-u8.c",
]
ALL_AVX_MICROKERNEL_SRCS = [
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u8.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u16.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u24.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-u32.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u8.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u16.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u24.c",
"src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-u32.c",
"src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-6f6m7l8c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-6f6m7l8c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-6f6m7l16c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-6f6m7l16c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-8f8m9l8c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-8f8m9l8c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-8f8m9l16c8s4r-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-8f8m9l16c8s4r-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-avx.c",
"src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx-acc2.c",
"src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u8.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u16.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u24.c",
"src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-u32.c",
"src/f32-gemm/gen/f32-gemm-1x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-1x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-3x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-4x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-4x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-5x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-5x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-6x8-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-6x16-minmax-avx-broadcast.c",
"src/f32-gemm/gen/f32-gemm-7x8-minmax-avx-broadcast.c",
"src/f32-gemminc/gen/f32-gemminc-1x8-minmax-avx-broadcast.c",
"src/f32-gemminc/gen/f32-gemminc-1x16-minmax-avx-broadcast.c",
"src/f32-gemminc/gen/f32-gemminc-3x16-minmax-avx-broadcast.c",
"src/f32-gemminc/gen/f32-gemminc-4x8-minmax-avx-broadcast.c",
"src/f32-gemminc/gen/f32-gemminc-4x16-minmax-avx-broadcast.c",
"src/f32-gemminc/gen/f32-gemminc-5x8-minmax-avx-broadcast.c",
"src/f32-gemminc/gen/f32-gemminc-5x16-minmax-avx-broadcast.c",
"src/f32-gemminc/gen/f32-gemminc-6x8-minmax-avx-broadcast.c",
"src/f32-gemminc/gen/f32-gemminc-6x16-minmax-avx-broadcast.c",
"src/f32-gemminc/gen/f32-gemminc-7x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-1x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-1x16-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-3x16-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-4x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-4x16-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-5x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-5x16-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-6x8-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-6x16-minmax-avx-broadcast.c",
"src/f32-igemm/gen/f32-igemm-7x8-minmax-avx-broadcast.c",
"src/f32-prelu/gen/f32-prelu-avx-2x8.c",
"src/f32-prelu/gen/f32-prelu-avx-2x16.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x16-minmax-avx-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-2x16-minmax-avx-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x16-minmax-avx-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x16-minmax-avx-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x16-minmax-avx-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x16-minmax-avx-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-7x16-minmax-avx-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-8x16-minmax-avx-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16-minmax-avx-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x16-minmax-avx-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x16-minmax-avx-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16-minmax-avx-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x16-minmax-avx-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x16-minmax-avx-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x16-minmax-avx-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x16-minmax-avx-broadcast.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u8.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u16.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u24.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-u32.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u8.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u16.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u24.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-u32.c",
"src/f32-rdsum/gen/f32-rdsum-7p7x-minmax-avx-c16.c",
"src/f32-rdsum/gen/f32-rdsum-7p7x-minmax-avx-c32.c",
"src/f32-rdsum/gen/f32-rdsum-7p7x-minmax-avx-c64.c",
"src/f32-rminmax/gen/f32-rmax-avx-u8.c",
"src/f32-rminmax/gen/f32-rmax-avx-u16-acc2.c",
"src/f32-rminmax/gen/f32-rmax-avx-u24-acc3.c",
"src/f32-rminmax/gen/f32-rmax-avx-u32-acc2.c",
"src/f32-rminmax/gen/f32-rmax-avx-u32-acc4.c",
"src/f32-rminmax/gen/f32-rmin-avx-u8.c",
"src/f32-rminmax/gen/f32-rmin-avx-u16-acc2.c",
"src/f32-rminmax/gen/f32-rmin-avx-u24-acc3.c",
"src/f32-rminmax/gen/f32-rmin-avx-u32-acc2.c",
"src/f32-rminmax/gen/f32-rmin-avx-u32-acc4.c",
"src/f32-rminmax/gen/f32-rminmax-avx-u8.c",
"src/f32-rminmax/gen/f32-rminmax-avx-u16-acc2.c",
"src/f32-rminmax/gen/f32-rminmax-avx-u24-acc3.c",
"src/f32-rminmax/gen/f32-rminmax-avx-u32-acc2.c",
"src/f32-rminmax/gen/f32-rminmax-avx-u32-acc4.c",
"src/f32-rsum/gen/f32-rsum-avx-u8.c",
"src/f32-rsum/gen/f32-rsum-avx-u16-acc2.c",
"src/f32-rsum/gen/f32-rsum-avx-u24-acc3.c",
"src/f32-rsum/gen/f32-rsum-avx-u32-acc2.c",
"src/f32-rsum/gen/f32-rsum-avx-u32-acc4.c",
"src/f32-vbinary/gen/f32-vadd-minmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vadd-minmax-avx-u16.c",
"src/f32-vbinary/gen/f32-vaddc-minmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vaddc-minmax-avx-u16.c",
"src/f32-vbinary/gen/f32-vdiv-minmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vdiv-minmax-avx-u16.c",
"src/f32-vbinary/gen/f32-vdivc-minmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vdivc-minmax-avx-u16.c",
"src/f32-vbinary/gen/f32-vmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vmax-avx-u16.c",
"src/f32-vbinary/gen/f32-vmaxc-avx-u8.c",
"src/f32-vbinary/gen/f32-vmaxc-avx-u16.c",
"src/f32-vbinary/gen/f32-vmin-avx-u8.c",
"src/f32-vbinary/gen/f32-vmin-avx-u16.c",
"src/f32-vbinary/gen/f32-vminc-avx-u8.c",
"src/f32-vbinary/gen/f32-vminc-avx-u16.c",
"src/f32-vbinary/gen/f32-vmul-minmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vmul-minmax-avx-u16.c",
"src/f32-vbinary/gen/f32-vmulc-minmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vmulc-minmax-avx-u16.c",
"src/f32-vbinary/gen/f32-vrdivc-minmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vrdivc-minmax-avx-u16.c",
"src/f32-vbinary/gen/f32-vrsubc-minmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vrsubc-minmax-avx-u16.c",
"src/f32-vbinary/gen/f32-vsqrdiff-avx-u8.c",
"src/f32-vbinary/gen/f32-vsqrdiff-avx-u16.c",
"src/f32-vbinary/gen/f32-vsqrdiffc-avx-u8.c",
"src/f32-vbinary/gen/f32-vsqrdiffc-avx-u16.c",
"src/f32-vbinary/gen/f32-vsub-minmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vsub-minmax-avx-u16.c",
"src/f32-vbinary/gen/f32-vsubc-minmax-avx-u8.c",
"src/f32-vbinary/gen/f32-vsubc-minmax-avx-u16.c",
"src/f32-vclamp/gen/f32-vclamp-avx-u8.c",
"src/f32-vclamp/gen/f32-vclamp-avx-u16.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u8.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u16.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u24.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u32.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u40.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-u48.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u8.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u16.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u24.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u32.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u40.c",
"src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-u48.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-u8.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-u16.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-u24.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-u32.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-u40.c",
"src/f32-velu/gen/f32-velu-avx-rr2-p6-u48.c",
"src/f32-vhswish/gen/f32-vhswish-avx-u8.c",
"src/f32-vhswish/gen/f32-vhswish-avx-u16.c",
"src/f32-vlrelu/gen/f32-vlrelu-avx-u8.c",
"src/f32-vlrelu/gen/f32-vlrelu-avx-u16.c",
"src/f32-vrelu/gen/f32-vrelu-avx-u8.c",
"src/f32-vrelu/gen/f32-vrelu-avx-u16.c",
"src/f32-vrnd/gen/f32-vrndd-avx-u8.c",
"src/f32-vrnd/gen/f32-vrndd-avx-u16.c",
"src/f32-vrnd/gen/f32-vrndne-avx-u8.c",
"src/f32-vrnd/gen/f32-vrndne-avx-u16.c",
"src/f32-vrnd/gen/f32-vrndu-avx-u8.c",
"src/f32-vrnd/gen/f32-vrndu-avx-u16.c",
"src/f32-vrnd/gen/f32-vrndz-avx-u8.c",
"src/f32-vrnd/gen/f32-vrndz-avx-u16.c",
"src/f32-vrsqrt/gen/f32-vrsqrt-avx-rsqrt-u8.c",
"src/f32-vrsqrt/gen/f32-vrsqrt-avx-rsqrt-u16.c",
"src/f32-vrsqrt/gen/f32-vrsqrt-avx-rsqrt-u32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u40.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u48.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u56.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u64.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u72.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-u80.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u40.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u48.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u56.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u64.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u72.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-u80.c",
"src/f32-vsqrt/gen/f32-vsqrt-avx-rsqrt-u8.c",
"src/f32-vsqrt/gen/f32-vsqrt-avx-rsqrt-u16.c",
"src/f32-vsqrt/gen/f32-vsqrt-avx-rsqrt-u32.c",
"src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-u8.c",
"src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-u16.c",
"src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr1-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-nr2-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-div-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-div-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-div-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-div-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-nr-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-nr-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-nr-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx-rational-9-6-nr-u32.c",
"src/f32-vunary/gen/f32-vabs-avx-u8.c",
"src/f32-vunary/gen/f32-vabs-avx-u16.c",
"src/f32-vunary/gen/f32-vneg-avx-u8.c",
"src/f32-vunary/gen/f32-vneg-avx-u16.c",
"src/f32-vunary/gen/f32-vsqr-avx-u8.c",
"src/f32-vunary/gen/f32-vsqr-avx-u16.c",
"src/math/f32-exp-avx-rr2-p5.c",
"src/math/f32-expm1minus-avx-rr2-lut4-p4-perm.c",
"src/math/f32-expm1minus-avx-rr2-lut16-p3.c",
"src/math/f32-expm1minus-avx-rr2-p6.c",
"src/math/f32-sigmoid-avx-rr2-lut64-p2-div.c",
"src/math/f32-sigmoid-avx-rr2-p5-div.c",
"src/math/f32-sigmoid-avx-rr2-p5-nr1.c",
"src/math/f32-sigmoid-avx-rr2-p5-nr2.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr1-lut8-p4h3ps-div.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-div.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-nr1.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr1-p6h5ts-nr2.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h2ts-nr1.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h2ts-nr2.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ps-nr1.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ps-nr2.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ts-nr1.c",
"src/math/gen/f32-tanh-avx-expm1minus-rr2-lut8-p4h3ts-nr2.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-4x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-1x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-1x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-2x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-2x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-3x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-3x4c8-minmax-avx-ld128.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-4x4c8-minmax-avx-ld64.c",
"src/qd8-f32-qc8w-igemm/gen/qd8-f32-qc8w-igemm-4x4c8-minmax-avx-ld128.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul16.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul16.c",
"src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul16.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-avx-mul32.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul16.c",
"src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx-mul32.c",
"src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u8.c",
"src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u16.c",
"src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u24.c",
"src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx-u32.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx-mul16.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx-mul32.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx-mul16.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx-mul32.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx-mul16.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx-mul32.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx-mul16-add16.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx-mul16.c",
"src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx-mul32.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-avx-ld128.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-avx-ld64.c",
"src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-avx-ld128.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u8.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u16.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u24.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-u32.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u8.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u16.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u24.c",
"src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-u32.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u8.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u16.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u24.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-u32.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u8.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u16.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u24.c",
"src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-u32.c",
"src/qs8-vcvt/gen/qs8-vcvt-avx-u8.c",
"src/qs8-vcvt/gen/qs8-vcvt-avx-u16.c",
"src/qs8-vcvt/gen/qs8-vcvt-avx-u32.c",
"src/qs8-vhswish/gen/qs8-vhswish-avx-u8.c",
"src/qs8-vhswish/gen/qs8-vhswish-avx-u16.c",
"src/qs8-vhswish/gen/qs8-vhswish-avx-u32.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-avx-u8.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-avx-u16.c",
"src/qs8-vlrelu/gen/qs8-vlrelu-avx-u32.c",
"src/qs8-vmul/gen/qs8-vmul-minmax-fp32-avx-mul16-ld64-u8.c",
"src/qs8-vmul/gen/qs8-vmul-minmax-fp32-avx-mul16-ld64-u16.c",
"src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-avx-mul16-ld64-u8.c",
"src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-avx-mul16-ld64-u16.c",
"src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-u4.c",
"src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-u8.c",
"src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-u16.c",
"src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx-mul16.c",
"src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx-mul16.c",
"src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx-mul16.c",
"src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx-mul32.c",
"src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx-mul16.c",
"src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx-mul32.c",
"src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u8.c",
"src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u16.c",
"src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u24.c",
"src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-u32.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-avx-ld128.c",
"src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-avx-ld64.c",
"src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-avx-ld128.c",
"src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul16-ld64-u8.c",
"src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul16-ld64-u16.c",
"src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul32-ld32-u8.c",
"src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul32-ld32-u16.c",
"src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul16-ld64-u8.c",
"src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul16-ld64-u16.c",
"src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul32-ld32-u8.c",
"src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul32-ld32-u16.c",
"src/qu8-vcvt/gen/qu8-vcvt-avx-u8.c",
"src/qu8-vcvt/gen/qu8-vcvt-avx-u16.c",
"src/qu8-vcvt/gen/qu8-vcvt-avx-u32.c",
"src/qu8-vhswish/gen/qu8-vhswish-avx-u8.c",
"src/qu8-vhswish/gen/qu8-vhswish-avx-u16.c",
"src/qu8-vhswish/gen/qu8-vhswish-avx-u32.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-avx-u8.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-avx-u16.c",
"src/qu8-vlrelu/gen/qu8-vlrelu-avx-u32.c",
"src/qu8-vmul/gen/qu8-vmul-minmax-fp32-avx-mul16-ld64-u8.c",
"src/qu8-vmul/gen/qu8-vmul-minmax-fp32-avx-mul16-ld64-u16.c",
"src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-avx-mul16-ld64-u8.c",
"src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-avx-mul16-ld64-u16.c",
"src/x8-lut/gen/x8-lut-avx-u16.c",
"src/x8-lut/gen/x8-lut-avx-u32.c",
"src/x8-lut/gen/x8-lut-avx-u48.c",
"src/x8-lut/gen/x8-lut-avx-u64.c",
"src/x32-packw/gen/x32-packw-x8-gemm-goi-avx-u4-prfm.c",
"src/x32-packw/gen/x32-packw-x8-gemm-goi-avx-u4.c",
"src/x32-packw/gen/x32-packw-x8s4-gemm-goi-avx-u4-prfm.c",
"src/x32-packw/gen/x32-packw-x8s4-gemm-goi-avx-u4.c",
"src/x32-packw/gen/x32-packw-x16-gemm-goi-avx-u4-prfm.c",
"src/x32-packw/gen/x32-packw-x16-gemm-goi-avx-u4.c",
"src/x32-packw/gen/x32-packw-x16s4-gemm-goi-avx-u4-prfm.c",
"src/x32-packw/gen/x32-packw-x16s4-gemm-goi-avx-u4.c",
"src/x32-transposec/gen/x32-transposec-8x8-multi-mov-avx.c",
"src/x32-transposec/gen/x32-transposec-8x8-multi-switch-avx.c",
"src/x32-transposec/gen/x32-transposec-8x8-reuse-mov-avx.c",
"src/x32-transposec/gen/x32-transposec-8x8-reuse-multi-avx.c",
"src/x32-transposec/gen/x32-transposec-8x8-reuse-switch-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-multi-mov-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-multi-multi-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-multi-switch-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-reuse-mov-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-reuse-multi-avx.c",
"src/x64-transposec/gen/x64-transposec-4x4-reuse-switch-avx.c",
]
ALL_AVX2_MICROKERNEL_SRCS = [
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-1x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-1x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-3x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-4x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-4x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-5x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-5x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-6x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-gemm/gen/f16-f32acc-gemm-7x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-1x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-1x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-3x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-4x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-4x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-5x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-5x16-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-6x8-minmax-avx2-broadcast.c",
"src/f16-f32acc-igemm/gen/f16-f32acc-igemm-7x8-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-1x8-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-1x16-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-3x16-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-4x8-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-4x16-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-5x8-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-5x16-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-6x8-minmax-avx2-broadcast.c",
"src/f16-gemm/gen/f16-gemm-7x8-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-1x8-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-1x16-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-3x16-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-4x8-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-4x16-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-5x8-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-5x16-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-6x8-minmax-avx2-broadcast.c",
"src/f16-igemm/gen/f16-igemm-7x8-minmax-avx2-broadcast.c",
"src/f16-pavgpool/f16-pavgpool-9p8x-minmax-avx2-c8.c",
"src/f16-pavgpool/f16-pavgpool-9x-minmax-avx2-c8.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u16-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u16.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u32-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u32-acc4.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u32.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u40-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u40-acc5.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u40.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u48-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u48-acc3.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u48.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u64-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u64-acc4.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u64.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u72-acc3.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u72.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u80-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u80-acc5.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u80.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u96-acc2.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u96-acc3.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u96-acc6.c",
"src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-u96.c",
"src/f16-velu/gen/f16-velu-avx2-rr1-p3-u8.c",
"src/f16-velu/gen/f16-velu-avx2-rr1-p3-u16.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u8.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u16.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u24.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u32.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u40.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u48.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u56.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-u64.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u8.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u16.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u24.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u32.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u40.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u48.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u56.c",
"src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-u64.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u8.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u16.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u24.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u32.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u40.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u48.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u56.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u64.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u72.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-div-u80.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u8.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u16.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u24.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u32.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u40.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u48.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u56.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u64.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u72.c",
"src/f16-vtanh/gen/f16-vtanh-avx2-expm1minus-rr1-p3h2ts-rcp-u80.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x16-minmax-avx2-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-2x16-minmax-avx2-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x16-minmax-avx2-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x16-minmax-avx2-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x16-minmax-avx2-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x16-minmax-avx2-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-7x16-minmax-avx2-broadcast.c",
"src/f32-qc4w-gemm/gen/f32-qc4w-gemm-8x16-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16s4-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x16-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x16s4-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x16-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x16s4-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16s4-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x16-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x16s4-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x16-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x16s4-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x8-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x16-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x8-minmax-avx2-broadcast.c",
"src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x16-minmax-avx2-broadcast.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-u16.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-u32.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-u48.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx2-u64.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-u16.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-u32.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-u48.c",
"src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx2-u64.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u32-acc2.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u32-acc4.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u32.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u64-acc2.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u64-acc4.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u64.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u72-acc3.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u72.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u80-acc2.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u80-acc5.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u80.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u96-acc2.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u96-acc3.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u96-acc6.c",
"src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx2-p5-u96.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u32-acc2.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u32-acc4.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u32.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u64-acc2.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u64-acc4.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u64.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u72-acc3.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u72.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u80-acc2.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u80-acc5.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u80.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u96-acc2.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u96-acc3.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u96-acc6.c",
"src/f32-raddextexp/gen/f32-raddextexp-avx2-p5-u96.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u32-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u32-acc4.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u32.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u64-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u64-acc4.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u64.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u72-acc3.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u72.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u80-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u80-acc5.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u80.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u96-acc2.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u96-acc3.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u96-acc6.c",
"src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx2-rr1-p5-u96.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u8.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u16.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u24.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u32.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u40.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u48.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u56.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u64.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u72.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut4-p4-perm-u80.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u8.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u16.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u24.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u32.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u40.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u48.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u56.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u64.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u72.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut8-p4-perm-u80.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u8.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u16.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u24.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u32.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u40.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u48.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u56.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u64.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u72.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-lut16-p3-gather-u80.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-u8.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-u16.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-u24.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-u32.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-u40.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-u48.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-u56.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-u64.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-u72.c",
"src/f32-velu/gen/f32-velu-avx2-rr1-p6-u80.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u8.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u16.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u24.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u32.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u40.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u48.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u56.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u64.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u72.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u80.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u88.c",
"src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx2-p5-u96.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u8.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u16.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u24.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u32.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u40.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u48.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u56.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u64.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u72.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u80.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u88.c",
"src/f32-vscaleextexp/gen/f32-vscaleextexp-avx2-p5-u96.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u40.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u48.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u56.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u64.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u72.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-div-u80.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u40.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u48.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u56.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u64.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u72.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr1fma-u80.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u8.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u16.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u24.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u32.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u40.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u48.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u56.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u64.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u72.c",
"src/f32-vsigmoid/gen/f32-vsigmoid-avx2-rr1-p5-nr2fma-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-div-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-div-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-div-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1-u80.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u8.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u16.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u24.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u32.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u40.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u48.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u56.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u64.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u72.c",
"src/f32-vtanh/gen/f32-vtanh-avx2-expm1minus-rr1-p6h5ts-nr1adj-u80.c",
"src/math/f16-expm1minus-avx2-rr1-p2.c",
"src/math/f16-expm1minus-avx2-rr1-p3.c",
"src/math/f16-expminus-avx2-rr1-p2.c",
"src/math/f16-expminus-avx2-rr1-p3.c",
"src/math/f16-sigmoid-avx2-rr1-p2-div.c",
"src/math/f16-sigmoid-avx2-rr1-p2-rcp.c",
"src/math/f16-sigmoid-avx2-rr1-p3-div.c",
"src/math/f16-sigmoid-avx2-rr1-p3-rcp.c",
"src/math/f32-exp-avx2-rr2-lut8-p3-perm.c",
"src/math/f32-exp-avx2-rr2-lut8-p4-perm.c",
"src/math/f32-exp-avx2-rr2-p5.c",
"src/math/f32-expm1minus-avx2-rr1-lut4-p4-perm.c",
"src/math/f32-expm1minus-avx2-rr1-lut8-p4-perm.c",
"src/math/f32-expm1minus-avx2-rr1-lut16-p3-gather.c",
"src/math/f32-expm1minus-avx2-rr1-p6.c",
"src/math/f32-expminus-avx2-rr1-p5.c",
"src/math/f32-expminus-avx2-rr2-p5.c",
"src/math/f32-extexp-avx2-p5.c",
"src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-div.c",
"src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-nr1fma.c",
"src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-nr2fma1adj.c",
"src/math/f32-sigmoid-avx2-rr1-lut64-p2-gather-nr2fma.c",
"src/math/f32-sigmoid-avx2-rr1-p5-div.c",
"src/math/f32-sigmoid-avx2-rr1-p5-nr1fma.c",
"src/math/f32-sigmoid-avx2-rr1-p5-nr2fma.c",
"src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-div.c",
"src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-nr1fma.c",
"src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-nr2fma1adj.c",
"src/math/f32-sigmoid-avx2-rr2-lut64-p2-gather-nr2fma.c",
"src/math/f32-sigmoid-avx2-rr2-p5-div.c",
"src/math/f32-sigmoid-avx2-rr2-p5-nr1fma.c",
"src/math/f32-sigmoid-avx2-rr2-p5-nr2fma.c",
"src/math/gen/f16-tanh-avx2-expm1minus-rr1-p3h2ts-div.c",
"src/math/gen/f16-tanh-avx2-expm1minus-rr1-p3h2ts-rcp.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-div.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-gather-div.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-gather-nr1.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-gather-nr1adj.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-perm-div.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-perm-nr1.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-lut8-p4h3ps-perm-nr1adj.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-p6h5ts-div.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-p6h5ts-nr1.c",
"src/math/gen/f32-tanh-avx2-expm1minus-rr1-p6h5ts-nr1adj.c",
"src/qd8-f16-qc4w-gemm/gen/qd8-f16-qc4w-gemm-1x8c8-minmax-avx2.c",
"src/qd8-f16-qc4w-gemm/gen/qd8-f16-qc4w-gemm-2x8c8-minmax-avx2.c",
"src/qd8-f16-qc4w-gemm/gen/qd8-f16-qc4w-gemm-3x8c8-minmax-avx2.c",
"src/qd8-f16-qc4w-gemm/gen/qd8-f16-qc4w-gemm-4x8c8-minmax-avx2.c",
"src/qd8-f16-qc8w-gemm/gen/qd8-f16-qc8w-gemm-1x8c8-minmax-avx2.c",
"src/qd8-f16-qc8w-gemm/gen/qd8-f16-qc8w-gemm-2x8c8-minmax-avx2.c",
"src/qd8-f16-qc8w-gemm/gen/qd8-f16-qc8w-gemm-3x8c8-minmax-avx2.c",
"src/qd8-f16-qc8w-gemm/gen/qd8-f16-qc8w-gemm-4x8c8-minmax-avx2.c",
"src/qd8-f16-qc8w-igemm/gen/qd8-f16-qc8w-igemm-1x8c8-minmax-avx2.c",
"src/qd8-f16-qc8w-igemm/gen/qd8-f16-qc8w-igemm-2x8c8-minmax-avx2.c",
"src/qd8-f16-qc8w-igemm/gen/qd8-f16-qc8w-igemm-3x8c8-minmax-avx2.c",
"src/qd8-f16-qc8w-igemm/gen/qd8-f16-qc8w-igemm-4x8c8-minmax-avx2.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-1x8c8-minmax-avx2.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-2x8c8-minmax-avx2.c",
"src/qd8-f32-qc4w-gemm/gen/qd8-f32-qc4w-gemm-3x8c8-minmax-avx2.c",