Feature request: better control on which gates to use for building circuits from table/expression

[yowshi]

The ability to specify a selection of gates when minimizing/building a circuit from the analyse circuit menu. So instead of just NAND gates or all gates you could specify a selection like NOT, OR, NOR gates alongside specifying whether or not you want to use only two input gates.

[maehne]

As Logisim-evolution is an educational tool, the choices for minimising a logic function were limited on purpose. It allows using Logisim-evolution in exam/lab settings, where students need to carry out still certain minimisation/typification tasks manually. This needs to get considered when proposing/implementing this additional flexibility.

[maehne]

What is the opinion of other Logisim-evolution users/developers?

[JOGAsoft]

I would absolutely want more options. I think especially "build with NOR gates" should be an option since that's also in line with education (as NOR is the other universal gate). I think the options "NOT OR NOR" and "NOT AND NAND" also are good choices, since it reflects different common logic families such as ECL or TTL. I saw this thread just because I was frustrated by that I could not find a "NOR option".

[MadeInShineA]

Having a NOR only option would be great!

[maehne]

@JOGAsoft and @MadeInShineA: Thanks for your feedback. We are unfortunately still lacking feedback from some contributors, who use Logisim-evolution regularly in their classes. In our school, we would like to keep the current situation to facilitate our exam/lab settings.