Register Bank

[Mrlogisim]

Hi, I made a processor with a register bank where each register updates its data only when the clock rises edge, the problem is that the data reaches the register bank but even though the clock is high it does not update the selected registry value, what would be the problem?


In the last image, 7 should be saved in the cx register but it is not and I don't know what the problem is

[maehne]

The data registers in your screenshot are sensitive to the falling edge of clock. RegWrite needs to be active at the moment the registers sample their data inputs.

[Mrlogisim]

Yes, excuse me that was not the screenshot I wanted to show, now I edited it

[maehne]

The look of the components on the screenshot makes me believe that you maybe are not using the most recent version of Logisim-evolution. For comparison, in Logisim-evolution built from master, the demultiplexer looks like this:

Which version are you using? Can you share your design by attaching it in a ZIP archive to a message? Please also provide exact steps how to reproduce the issue you are observing.

[Mrlogisim]

unicycle processor.zip
I think my version of logisim evolution is 3.8.0 x86.msi, I didn't download the "all jar" version because it gave me a java error.
Steps:

1. I press the clock so that the first instruction is executed. The instruction is: addi, cx, r0, 7(6607 ROM)

2.As the registers have a rising edge, in theory the value 7 should be stored in the "cx" register.

3.but in "cx" nothing is stored, even though the record is enabled to save the data, it just stays there in "WriteData"

4.However, it is in the next cycle that the data is stored.

[maehne]

Thanks for your Logisim file and the additional screenshots. They make me believe that Logisim-evolution works correctly and that you are not experiencing a bug. To verify, I recommend you to simulate the registers block alone: When you set WriteData to some value, choose with rd the target register, and activate RegWrite, everything is set up for a write to the register. What is needed now is a transition from 0 to 1 (i.e., rising edge) on the Ck signal. The value ends up correctly in the register.

I think what you are observing is that the above-mentioned control signals get set after the rising edge. At this moment Ck is still 1. However, the register will sample its input only once Ck transitioned to 0 and then 1 again. This is standard behaviour for synchronous designs using a single clock. To get the value directly in the register, you would need to change their Trigger property to High Level, which would yield the behaviour of a data latch, which use in synchronous designs is not recommended.

[Mrlogisim]

Thank you very much for the help

[maehne]

@Mrlogisim: You are welcome!