Revamp the test vector component to add better support for sequential circuits testing

[zdimension]

Currently it's quite hard to test sequential circuits using Logisim's test engine.

[maehne]

@BFH-ktt1 and myself are not actively using this feature, but we are aware that other find it very useful. Ideas and PRs improving its usability for combinatoric and sequantial circuits and documentation are welcome. If the ideas become more concrete, don't hesitate making it an issue.

[maehne]

@BFH-ktt1 and myself reckon the need for improvements in this area. Any ideas what enhancements to Logisim-evolution functions might be needed to elegantly test sequential circuits are welcome! We have some ideas on our side, too, but we lack bandwidth to look further into it during the spring term.

[dtowell]

@rguyonneau it sounds like we have similar goals/desires. I currently use L-E --tty features to verify student submissions. I have working solution but it requires multiple executions to handle each circuit (exercise) and to verify the correct/acceptable gates were used. I would like the process to be quicker (require fewer executions) and additionally to provide additional info about the simulation process. Please see #1546

[ukuhne]

Any updates on this issue? I have the same application in mind (lab exercises on digital logic design). For combinational circuits, the test vectors work fine, but for sequential circuits, I had to do some extra stuff to make it work for me:

1. Simulate test bench circuit with golden (correct) circuit, save output in a file
2. Simulate test bench circuit with student's circuit (using the --substitute option), save output to a file
3. Compare the outputs

Currently, I have no way to define don't cares (signals not to compare).

I wrote a python script -- yes I did -- to convert the raw logisim simulation output into a vcd file viewable in GTKWave (see screenshot). It would be nice to have the sequential testing and waveform generation scriptable from the command line and to directly export a vcd.

All this are just ideas. I haven't looked into the source code of LE yet, and I don't know how easy this would be or what the current priorities are.

[rguyonneau]

Sorry, I did not manage to find time to check this out...

[maehne]

@ukuhne: Thanks for sharing your approach!

Currently, I have no way to define don't cares (signals not to compare).

Indeed, handling don't cares is important to be able to check/evaluate automatically sequential circuits of students.

Currently, the best approach, I can see is to netlist the student's submission to VHDL and embed it into an automated test bench together with a reference circuit for comparison and doing black box verification.