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I tried Slang for a while but gave up as there's a lot of complexity to transform its AST into something NVC can use internally. Plus I don't want to add too many external dependencies and Slang is written in a style of template-heavy C++ that is incredibly slow to compile and link (I find long compile times quite frustrating). For now I just want to do something very simple to test the idea for adding some level of Verilog support on top of the existing vcode IR and simulator. In the future I might revisit the idea of using a proper front-end, but for now I'd rather just have everything in one repository with the same coding style. I looked at Verible briefly and it's using Bison too (as does Iverilog). FWIW Verilog is much simpler to parse than VHDL so it's possible to use a parser generator. |
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Some basic Verilog-95 support would be very useful in a few projects we have were the FPGA vendor only provides Verilog libraries, requiring us to use mixed-language licenses for the commercial tools. |
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OK, I see. Its always a "build or use" question. But I guess that if you add basic Verilog support, users will want more :D |
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This is a continuation of : #558
Hello @nickg , I have noticed that you added a stub of Verilog compiler along with yacc based parsing.
IIRC from the last discussion, you planned to use third-party parser (UHDM / Verible / Slang) to parse
verilog. Did you change your mind, and build the parser by yourself :) ?
This is in no way meant to push about the Verilog support, I am just curious, since I am now starting
to slowly understand more from NVCs code base :)
That being said, parsing Verilog (and System Verilog) must be a huge effort.
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