Verilog - Support celldefine, endcelldefine, ifdef and else

[Blebowski]

Hi,

after seeing https://github.com/nickg/nvc/issues/808 I gave it a shot at compiling Verilog standard cell libraries I have available for a PDK that we use. I see couple of macros unsupported:

** Warning: macro celldefine undefined
      > /projects/pdks/fancy_pdk_name_that_is_unfortunately_under_nda.v:1671
      |
 1671 | `celldefine
      | ^^^^^^^^^^^

** Warning: macro endcelldefine undefined
      > /projects/pdks/fancy_pdk_name_that_is_unfortunately_under_nda.v:1669
      |
 1669 | `endcelldefine
      | ^^^^^^^^^^^^^^

** Warning: macro ifdef undefined
      > /projects/pdks/fancy_pdk_name_that_is_unfortunately_under_nda.v:1676
      |
 1676 |    `ifdef FUNCTIONAL  //  functional //
      |    ^^^^^^

** Warning: macro else undefined
      > /projects/pdks/fancy_pdk_name_that_is_unfortunately_under_nda.v:1680
      |
 1680 |    `else
      |    ^^^^^

** Warning: macro endif undefined
      > /projects/pdks/fancy_pdk_name_that_is_unfortunately_under_nda.v:1807
      |
 1807 |    `endif
      |    ^^^^^^

Tried to put together MVP example of the cell from PDK:

`timescale 1ns/1ps

`celldefine
module AND_GATE(A,B,Y);
input A, B;
output Y;

   `ifdef FUNCTIONAL  //  functional //

        AND_GATE_func AND_GATE_behav_inst(.A(A),.B(B),.Y(Y));

   `else

        AND_GATE_func AND_GATE_behav_inst(.A(A),.B(B),.Y(Y));

   specify

        // specify_block_begin

        if(B===1'b0)
          // comb arc A --> Y
          (A => Y) = (1.0,1.0);

        if(B===1'b1)
          // comb arc A --> Y
          (A => Y) = (1.0,1.0);

        if(A===1'b0)
          // comb arc B --> Y
          (B => Y) = (1.0,1.0);

        if(A===1'b1)
          // comb arc B --> Y
          (B => Y) = (1.0,1.0);

     endspecify

   `endif

endmodule
`endcelldefine

Note that this has several other issues (non-ANSI port declaration, specify blocks),
but its the most rudimentary cell definition I could create. Feel free to close/do whatever with the issue if
it is too soon and the verilog implementation is not yet there.