Neorv32 in Space with Skudo.tech

[Skudo-HSM]

Greetings, fellow tech enthusiasts!

Today's focus is the use of the Neorv32 RISC-V core, developed by SN and this community, in our latest space endeavour. This post serves as both a testament to and an appreciation of your ground-breaking work behind this technology, which has proven instrumental in our satellite’s data processing capabilities.

RISC-V Core in Space: The Technical Edge
The integration of the RISC-V core into our project (tested on a real satellite system) was a decision driven by specific technical needs. Given the requirements for minimal power consumption and simplicity in its integration, your RISC-V core, known for its efficiency and documentation, was a natural fit. Its implementation in Verilog played a crucial role in ensuring adaptability.

In orbit, housed within the Cyclone-V FPGA setup on board of the ESA's OPS-SAT, the core’s primary responsibility was image processing. Leveraging its design, the core efficiently handled algorithms for image processing (marking clouds in yellow on a photo taken by the satellite), crucial for our satellite's mission. The mission was successfully executed towards the end of October 2023.

Verilog Implementation: Precision and Reliability
The choice of Verilog for designing the RISC-V core was pivotal. It facilitated extensive ground-based simulation and testing in our ground setup and easy integration in our existing HSM/FPGA setup, a crucial step given the inaccessibility of space-based systems for physical debugging or updates. The core's performance in orbit validated the efficacy of its Verilog-based design.

Acknowledging the Verilog NEORV32 RISC-V Team
To the team behind the RISC-V core’s Verilog design: your work has directly contributed to the success of a short but yet complex space mission. The core’s operational success in the harsh conditions of space is a testament to the precision of your design and understanding of its capabilities.

The success of the RISC-V core in this mission exemplifies how well-designed hardware can significantly enhance satellite functionality. This achievement underlines the importance of meticulous design work and the capability of Verilog in meeting the demanding requirements of space technology. To the Verilog RISC-V team, your contributions have been integral to our project's success and have set a benchmark for future space technology developments.

A short video explanatory of Skudo's space experiment can be found here: https://vimeo.com/880805004

Please note, licensing requirements have been meticulously followed in our documents and due credits have been given as required.
www.skudo.tech

[stnolting]

Hey @Skudo-HSM.

This is so amazing!!! Thank so much for sharing this! :)

I'm curious. 😅

Did you do a complete re-implementation of the core using Verilog or did your use neorv32-verilog) as starting point?

Did you add some kind of radiation-hardening like TMR or ECC?

How did you integrate/couple your security hardware module(s)?

Could you give some more details about the actual application/algorithm the core is processing?

I'll have a look at the stars tonight with big a smile 😄

[Skudo-HSM]

Hey @stnolting
glad you liked it :)

It was original VHDL almost entirely, only new cores specific to the test environment was done in Verilog and wrapped as VHDL components.
We replaced the instruction memory implementation in order to have the R5 code reloaded by external circuitry. And we had to replace data memory implementation too, for the reasons we don't clearly understand the Quartus had issues inferring hardware memory blocks within large design with both default and legacy memory implementations. The data memory was inferred ok in test environments, but within the whole system the Quartus gave up and tried to express it with registers.
It was demoed on the OPS-SAT which uses a MitySOM SoC with a plain Cyclone-V (no space rad stuff :)
The modules were available as peripherals on the wishbone bus, and we made in Verilog the adapter translating requests between R5 Wishbone bus and the hosting system bus.
Also we didn't interact RISC-V with HSM as the aim was to demo the two different approach (image processing on one and encryption on the other). The image processing was very simple (just for the sake of demonstration): we marked the clouds in yellow (see the Vimeo link I shared above). The setup is used on the satellite for a limited amount of time, also because the satellite is at its EOL :) But we are working on more projects for the future.

[stnolting]

And we had to replace data memory implementation too, for the reasons we don't clearly understand the Quartus had issues inferring hardware memory blocks within large design with both default and legacy memory implementations.

That's interesting. I have never worked with MAX10 FPGAs but I've heard that people hat some troubles with the block RAMs there. I think the initialization via bitstream is somehow a bit more non-intuitive there?! 🤔

It was demoed on the OPS-SAT which uses a MitySOM SoC with a plain Cyclone-V (no space rad stuff :)

Is the orbit "low enough" that you do not need to worry about radiation-caused bit flips? Or do you have some kind of heavy shielding around the board? How about ECC memories? Is that required?

The image processing was very simple (just for the sake of demonstration): we marked the clouds in yellow (see the Vimeo link I shared above).

Can you say something more about that (the algorithm)? What kind of ISA configuration do you use? How much percent of the FPGA is used by the processor itself and at what frequency is used to clock it?

The setup is used on the satellite for a limited amount of time, also because the satellite is at its EOL :)

Is it still up there or has it already come down as a shooting star? 😅

Again, thank you very much for sharing this! 👍

[mkgin]

Is it still up there or has it already come down as a shooting star? 😅

Haven't been able to find anything official or authoritative about OPSSAT status, but at least a couple months ago, still up at around 400km.

I found this which seems to indicate it will come down sometime soon.

[stnolting]

Interesting data! Thanks for sharing!

[Skudo-HSM]

Yeah, the sat is EOL ... on 18.2 the head of the program at ESA wrote: "I am writing to inform you that this weekend OPS-SAT-1 dipped below the 400 km altitude boundary. We were working hard to delay the associated acceleration in altitude loss but so far we have not been successful. As we descend further, the aerodynamic disturbance torques will increase and we are not sure how much attitude control we can expect. It is therefore wise that we all plan for a potential end of experimentation in the next couple of months. Let me take this opportunity to thank you all for your support over the last 4 years. It has been quite a ride."
RIP

[stnolting]

RIP 😭😅

Btw, is there something like a (public) mission report?

[Skudo-HSM]

Not that I am aware of, I will let you if I come across something.

[stnolting]

Thank your very much! :)