Stream Link Interfaces for AXI DMA

[Giorgio122]

Goodmorning, I was trying to use the Stream Link Interface extension to be able to communicate with the AXI DMA ip provided by Xilinx/AMD. My question is related to how the signals are managed: in the user guide it is said that the Stream Link interface is AXI4-stream compatibile, but 2 signals are missing in this case, these being the TLAST and TKEEP. Supposing that TKEEP might be left and binded to all 1s (correct me if i'm wrong), the TLAST has to be correctly driven in order for the DMA to work correctly. So, my question is: I have to generate it in the Stream Link Interface since it is not present, right?
Thanks!

[stnolting]

Hey @Giorgio122!

in the user guide it is said that the Stream Link interface is AXI4-stream compatibile, but 2 signals are missing in this case, these being the TLAST and TKEEP

Well, yes, these signals are implemented within the SLINK module. However, I still think this can be considered "AXI4-compatible" as those signals are listed as optional in the AXI specs (if I remember correctly). 😅

Basically, the TLAST signal was not included into the SLINK module because we could not come up with a nice way to handle them from software/hardware side. There are no bits left when reading/writing from RX/to TX registers so how could we provide this additional status bit? 🤔

Anyway, you could use some spare signals from the GPIO controller to drive these missing signals manually.

[Giorgio122]

Perfect, thanks for the fast reply, it was extrimely useful! I'll try to drive them manually from GPIOs

[Giorgio122]

Goodmorning Stnolting,
sorry to bother once again. I managed to integrate Neorv32 Slink interface with the Xilinx DMA-IP, however I have some problems when sending data from the neorv to the DMA. In particular, I send 8 bytes of data towards the DMA through neorv32_slink_put(slink_data) function and then I trigger the TLAST signal via GPIO. However, when I try to read the data from the DMA, a strange behavior verifies. In particular, the output buffer where I store the received data will only populate arfter 64 bytes of data are sent (so, if I try to read after the first 2 iterations, the buffer will still be empty) and, as soon as some data is read, only the first 4 values that were sent will appear. Moreover, out of all the 32 bits transmitted every operations, only the first 8 LSBs are correctly received. I also attach a screenshot to display what happens. How can this happen? Is there a problem in my configurations or in the way I try to receive data in the DMA? Or is it possible that there are some problems during the transmission of data from Slink FIFOs towards the DMA?
The Slink interface has been configurate with a FIFO depth of 2.
Thanks for the attention,
Best regards.
Giorgio

[stnolting]

The precise timing of the tlast signal is crucial I think. This signal needs to be set during the very last "valid" cycle. So it needs to be set before making the very last transmission. So maybe the SLINK-internal FIFO buffer makes the precise signal timing much more complex (i.e. tlast is set too early or too late).

"Emulating" the tlast signal seems to be harder than I thought 🙈 So maybe we should add native hardware support to the SLINK module for this 😅

[stnolting]

I've started (re-)adding native hardware support for the tlast signals in #815 😉

[Giorgio122]

Thanks Stnolting for the fast reply, I will try these modifications as soon as possible and keep you updated.
Thanks for your work!