An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
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Updated
Sep 13, 2022 - C++
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
A MonteCarlo light propagation algorithm on a Xilinx FPGA using High Level Synthesis.
Convolutional Neural Networks for Verilog High-Level Synthesis
Small designs made using Catapult-based HLS (C++ / SystemC)
Laboratory exercises on cards with ARM, FPGA and sensors
Algorithmic Design of Digital Systems - Autumn Semester 2023 - Indian Institute of Technology Bombay
Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
Kiwi was developed at the University of Cambridge Computer Laboratory and Microsoft Research Limited, headed by **David Greaves (UoCCL)** and **Satnam Singh (MRL)**
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
Transpiles a subset of Python functions into synthesizable SystemVerilog.
Repository of DB4HLS. A database of design space exploration in high-level synthesis.
C++ code generation tools for real-time CPU or FPGA simulation solvers of electrical and power electronic systems. To cite this software publication: https://www.sciencedirect.com/science/article/pii/S2352711021000054
high abstraction synthesis
Design of High-Level Synthesis of Xilinx FFT IP core via FFT library
Personal blog on GitHub
Master thesis project - Comparing a FM Radio implementation in VHDL versus high-level synthesis (HLS).
[FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
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