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16 public repositories
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A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.
NEORV32 and a generic FAT file system called FatFs.
This repo contains the work developed in the SIEAV Master practices 🎓✏️📚
Updated
May 31, 2024
VHDL
Cross-platform compatible firmware download tool for use with the NEORV32 bootloader, written in Python
Updated
Sep 18, 2021
Python
🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
Updated
Nov 29, 2021
VHDL
Delivrables and code base from a CentraleSupéléc project
Updated
Jun 22, 2022
VHDL
🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
💾 FreeRTOS port for the NEORV32 RISC-V Processor.
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
Updated
May 31, 2024
Python
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
Updated
Mar 16, 2024
Shell
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
Updated
May 29, 2024
Verilog
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
Updated
May 27, 2024
VHDL
🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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