neorv32
Here are 17 public repositories matching this topic...
A LeNet-5 implementation using C language and FPGA, obtaining more performance (Hardware) together with greater versatility (Software), uniting the two worlds. Hardening the Software and Softening the Hardware, to something in between, like Molten Iron, so a Moltenware implementation.
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Jun 6, 2024 - C
Delivrables and code base from a CentraleSupéléc project
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Jun 22, 2022 - VHDL
A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.
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Nov 2, 2023 - C
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
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Jun 7, 2024 - Python
🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
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Nov 5, 2022 - VHDL
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
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Apr 4, 2024 - VHDL
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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Jun 6, 2024 - C
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