neorv32
Here are 17 public repositories matching this topic...
Delivrables and code base from a CentraleSupéléc project
-
Updated
Jun 22, 2022 - VHDL
🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
-
Updated
Nov 5, 2022 - VHDL
A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.
-
Updated
Nov 2, 2023 - C
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
-
Updated
Apr 4, 2024 - VHDL
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-
Updated
Jun 6, 2024 - C
A LeNet-5 implementation using C language and FPGA, obtaining more performance (Hardware) together with greater versatility (Software), uniting the two worlds. Hardening the Software and Softening the Hardware, to something in between, like Molten Iron, so a Moltenware implementation.
-
Updated
Jun 7, 2024 - C
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
-
Updated
Jun 7, 2024 - Python
Improve this page
Add a description, image, and links to the neorv32 topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the neorv32 topic, visit your repo's landing page and select "manage topics."