systemc
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Assignment from the Advanced Computer Architecture class.
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Nov 9, 2016 - C++
School assignment to make a client-server application in system C.
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Apr 12, 2017 - C
Trabalho 1 de Modelagem de Sistemas em Silício 1/2017
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May 15, 2017 - C++
Trabalho 3 de Modelagem de Sistemas em Silício 1/2017
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May 15, 2017 - C++
Trabalho 4 de Modelagem de Sistemas em Silício 1/2017
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May 15, 2017 - C++
An example of using Ramulator as memory model in a cycle-accurate SystemC Design
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Jun 30, 2017 - C++
SystemC implementation of a Viterbi encoder and decoder
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Jul 9, 2017 - C++
Projeto Final de Modelagem em Sistemas de Silício - 2017/1
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Jul 13, 2017 - Makefile
Trabalho Final de Modelagem de Sistemas em Silício 1/2017
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Jul 17, 2017 - Makefile
A simple testbench with two refmods using UVM Connect
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Aug 7, 2017 - SystemVerilog
A simple UVM testbench using UVM Connect and Octave
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Aug 7, 2017 - SystemVerilog
An N-bit counter module written in SystemC, VHDL and Verilog
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Oct 20, 2017 - VHDL
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