An HDL package manager.
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Updated
May 17, 2024 - Rust
An HDL package manager.
🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Digital logic design tool and simulator
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
learn the combinational and sequential logic circuit.
Haskell to VHDL/Verilog/SystemVerilog compiler
Common CORE of Network Development Kit (NDK)
The purpose of "Scratch VHDL" is to make reprogrammable logic design into child's play. Sounds ambitious.
VHDL grammar for tree-sitter parser generator
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
UNCode is an online platform for frequent practice and automatic evaluation of computer programming, Jupyter Notebooks and hardware description language (VHDL/Verilog) assignments. Also provides a pluggable interface with your existing LMS.
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