A package to generate Verilog/SystemVerilog code on Julia.
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Updated
Jun 2, 2024 - Julia
A package to generate Verilog/SystemVerilog code on Julia.
The repository hosts an ongoing project dedicated to the development of an implementation for the Advanced Encryption Standard (AES) 128-bit block cipher in UART communication. Please be advised that this project is currently in progress and subject to updates.
Verilator open-source SystemVerilog simulator and lint system
Python Templated Verilog
a verilog implementation of arbitrary waveform generator with Red Pitaya
learn the combinational and sequential logic circuit.
SystemVerilog compiler and language services
Norsk Data ND-120 CPU Design Documents. Modern Logisim and HDL implementation
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
RISC-V Linux SoC, marchID: 0x2b
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