Wrong timing with LSR abs,X / ROR abs,X / ROL abs,X for the 6502 CPU

[Archange427]

According to Lichty's book, 6502 datasheet and various other documents, these 3 opcodes :
LSR abs,X
ROR abs,X
ROL abs,X
(hex values: $5E / $3E / $7E)
have a duration of 7 cycles (in all cases) with 6502 and not 6.
6+ cycles are only for 65C02

Strangely ASL abs,X is OK.

[tomcw]

Thanks - I'll take a look.
It's easy to test with a Mockingboard's 6522.

Cross-referencing with Sather UTAIIe (or UTAII), page 4-24, Table 4.2 "6502 Instructions":

• ASL, LSR, ROL, ROR: for 'ABS X' => type 23 & 24
• Type 23 = ASL abs,x (NO PX) = 7 cycles
• Type 24 = ASL abs,x (PX) = 7 cycles

Cross-referencing with Sather UTAIIe, page 4-27, Table 4.3 "65C02 Instructions":

• ASL, LSR, ROL, ROR, DEC, INC: for 'ABS X' => type 23 & 24
• Type 23 = ASL abs,x (NO PX) = 6 cycles
• Type 24 = ASL abs,x (PX) = 7 cycles

[tomcw]

NB. AppleWin's 65C02 DEC/INC abs,x are the same for NO-PX or PX, so this needs fixing for the NO-PX case.

EDIT: No! As Nick says in #271:

INC abs,X and DEC abs,X were not optimized on the 65C02 - always 7 cycles.

[tomcw]

Also compare to #271, where you raised a similar issue, and I applied some fixes - but maybe not 100% correct!

[tomcw]

Tested on real h/w, unenhanced NMOS 6502:

300: A2 00 AD 04 C4 1E FF 20 AE 04 C4 00

.ORG $300
 LDX #0
 LDA $C404
 ASL $20FF,X
 LDX $C404
 BRK

insn	opcode	No PX	PX
asl abs,x	1E	7	7
rol abs,x	3E	7	7
lsr abs,x	5E	7	7
ror abs,x	7E	7	7

[tomcw]

@Archange427 - FYI, fixed in AppleWin 1.29.14.0 here.