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pb3_ise91.xise
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pb3_ise91.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="list_ch09_01_ps2_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="kcpsm3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="list_ch09_02_ps2_rxtx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="oneshot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="list_ch08_01_ps2_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="PB3_nexys_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="ram2k_8.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="VGAdrive.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="embedded_kcpsm3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="debounce.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="reg8b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="PROG_ROM.VHD" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="picoblaze3.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
<property xil_pn:name="Device" xil_pn:value="xc3s500e"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|PB3_Nexys_wrapper|PB3_Nexys_wrapper"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PB3_Nexys_wrapper"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="pb3_ise91"/>
<property xil_pn:name="PROP_mapSmartGuideFileName" xil_pn:value=""/>
<property xil_pn:name="PROP_parSmartGuideFileName" xil_pn:value=""/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs"/>
<property xil_pn:name="Package" xil_pn:value="fg320"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false"/>
<property xil_pn:name="Report Type" xil_pn:value="Error Report"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-XE VHDL"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value=""/>
</properties>
<bindings>
<binding xil_pn:location="/PB3_Nexys_wrapper" xil_pn:name="picoblaze3.ucf"/>
</bindings>
<libraries/>
<partitions>
<partition xil_pn:name="/PB3_Nexys_wrapper"/>
</partitions>
</project>