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Verilog Code Generation #4

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JohnKula opened this issue Feb 9, 2016 · 0 comments

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JohnKula commented Feb 9, 2016

Verilog code needs to be generated for the following modules:

IE, IF, JA, JB, JC, KA, KB, KC, MA, MB, MC, MD, ME, QB, RA, SF, TA, TB, TC, TD, TF, VA, VB, VL, VR, WA

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