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Cons: really awkward solution, may have unintended consequences
Swapping A/B on SN74LVC1T isn't feasible since this level shifter is asymmetric.
We have to implement (1) anyway to handle the existing devices; we must implement (2) or (3) for revD. What is not clear is whether or when revC4 will be designed, tested, and put into production.
The text was updated successfully, but these errors were encountered:
You can also power gate the VCCIO of the FPGA bank. Either using a power switch or having two 3v3 rail ( fed by another TLV75533PDRVR with a different EN line). Not saying it's a great option, but it's a fourth option.
Or shutdown the 3v3 to the IO drivers actually, that will also make them hi-z.
Either way, it's a bit similar to (2) since you can keep most of the design, but adds at least 1 part (albeit an already used one) but you can't keep the PCBs.
Many thanks for building and maintaining glasgow... I've got a question regarding this issue ... how practically does this affect using the current device revision (C3)? I'm new into this and can't reason about it if it's only an issue when there is some edge case hacking where you need to power the DUT or does it interfere using glasgow with some common setup? As this hasn't been detected during the different PCB version integration tests I guess it should be a minor concern, right?
This unfortunately happens because the reset state for the FPGA is pull-high, which translates to DIR=H (B=A), where A is FPGA-side and B is DUT-side.
Solutions:
Swapping A/B on SN74LVC1T isn't feasible since this level shifter is asymmetric.
We have to implement (1) anyway to handle the existing devices; we must implement (2) or (3) for revD. What is not clear is whether or when revC4 will be designed, tested, and put into production.
The text was updated successfully, but these errors were encountered: