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0017-Xtensa-Add-basic-support-for-inline-asm-constraints.patch
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0017-Xtensa-Add-basic-support-for-inline-asm-constraints.patch
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From bf9aa62ebb34c949cf3138577d546eec9fddebec Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov@espressif.com>
Date: Wed, 5 Apr 2023 00:58:43 +0300
Subject: [PATCH 017/158] [Xtensa] Add basic support for inline asm constraints
---
.../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 9 +++
.../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 3 +
llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 55 ++++++++++++++
llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 6 ++
llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 25 ++++++
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 76 +++++++++++++++++++
llvm/lib/Target/Xtensa/XtensaISelLowering.h | 21 +++++
7 files changed, 195 insertions(+)
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
index fe1dc0e2e483..10becc9e8c83 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
@@ -27,6 +27,15 @@ using namespace llvm;
#include "XtensaGenAsmWriter.inc"
+void XtensaInstPrinter::printAddress(unsigned Base, int64_t Disp,
+ raw_ostream &O) {
+ O << Disp;
+ if (Base) {
+ O << '(';
+ O << getRegisterName(Base) << ')';
+ }
+}
+
static void printExpr(const MCExpr *Expr, raw_ostream &OS) {
int Offset = 0;
const MCSymbolRefExpr *SRE;
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
index 46a35ae6f4e3..34d03569b9bc 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
@@ -35,6 +35,9 @@ public:
// Print the given operand.
static void printOperand(const MCOperand &MO, raw_ostream &O);
+ // Print an address
+ static void printAddress(unsigned Base, int64_t Disp, raw_ostream &O);
+
// Override MCInstPrinter.
void printRegName(raw_ostream &O, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
index 1935b86cfdc6..fb100a734e45 100644
--- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
@@ -14,6 +14,7 @@
//===----------------------------------------------------------------------===//
#include "XtensaAsmPrinter.h"
+#include "MCTargetDesc/XtensaInstPrinter.h"
#include "XtensaConstantPoolValue.h"
#include "XtensaMCInstLower.h"
#include "TargetInfo/XtensaTargetInfo.h"
@@ -216,6 +217,60 @@ void XtensaAsmPrinter::emitMachineConstantPoolValue(
}
}
+void XtensaAsmPrinter::printOperand(const MachineInstr *MI, int OpNo,
+ raw_ostream &O) {
+ const MachineOperand &MO = MI->getOperand(OpNo);
+
+ switch (MO.getType()) {
+ case MachineOperand::MO_Register:
+ case MachineOperand::MO_Immediate: {
+ XtensaMCInstLower Lower(MF->getContext(), *this);
+ MCOperand MC(Lower.lowerOperand(MI->getOperand(OpNo)));
+ XtensaInstPrinter::printOperand(MC, O);
+ break;
+ }
+ case MachineOperand::MO_GlobalAddress:
+ O << *getSymbol(MO.getGlobal());
+ break;
+ default:
+ llvm_unreachable("<unknown operand type>");
+ }
+
+ if (MO.getTargetFlags()) {
+ O << ")";
+ }
+}
+
+bool XtensaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+ const char *ExtraCode, raw_ostream &O) {
+ if (ExtraCode && *ExtraCode == 'n') {
+ if (!MI->getOperand(OpNo).isImm())
+ return true;
+ O << -int64_t(MI->getOperand(OpNo).getImm());
+ } else {
+ printOperand(MI, OpNo, O);
+ }
+ return false;
+}
+
+bool XtensaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
+ unsigned OpNo,
+ const char *ExtraCode,
+ raw_ostream &OS) {
+ XtensaInstPrinter::printAddress(MI->getOperand(OpNo).getReg(),
+ MI->getOperand(OpNo + 1).getImm(), OS);
+ return false;
+}
+
+void XtensaAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
+ raw_ostream &OS) {
+ OS << '%'
+ << XtensaInstPrinter::getRegisterName(MI->getOperand(opNum).getReg());
+ OS << "(";
+ OS << MI->getOperand(opNum + 1).getImm();
+ OS << ")";
+}
+
// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmPrinter() {
RegisterAsmPrinter<XtensaAsmPrinter> A(getTheXtensaTarget());
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
index 0ba80bc18c1c..50feaa0fcd2c 100644
--- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
@@ -38,6 +38,12 @@ public:
void emitInstruction(const MachineInstr *MI) override;
void emitConstantPool() override;
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override;
+ void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
+ bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+ const char *ExtraCode, raw_ostream &O) override;
+ bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
+ const char *ExtraCode, raw_ostream &OS) override;
+ void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
index 7522f97c0950..098265e1c07e 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
@@ -41,6 +41,9 @@ public:
// Override SelectionDAGISel.
void Select(SDNode *Node) override;
+ bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
+ std::vector<SDValue> &OutOps) override;
+
bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset,
int Scale) {
EVT ValTy = Addr.getValueType();
@@ -139,3 +142,25 @@ void XtensaDAGToDAGISel::Select(SDNode *Node) {
SelectCode(Node);
}
+
+bool XtensaDAGToDAGISel::SelectInlineAsmMemoryOperand(
+ const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
+ switch (ConstraintID) {
+ default:
+ llvm_unreachable("Unexpected asm memory constraint");
+ case InlineAsm::Constraint_m: {
+ SDValue Base, Offset;
+ // TODO
+ selectMemRegAddr(Op, Base, Offset, 4);
+ OutOps.push_back(Base);
+ OutOps.push_back(Offset);
+ return false;
+ }
+ case InlineAsm::Constraint_i:
+ case InlineAsm::Constraint_R:
+ case InlineAsm::Constraint_ZC:
+ OutOps.push_back(Op);
+ return false;
+ }
+ return false;
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 1b86f8846be3..d2e1c59f00e9 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -200,6 +200,82 @@ unsigned XtensaTargetLowering::getVaListSizeInBits(const DataLayout &DL) const {
return 3 * 4;
}
+//===----------------------------------------------------------------------===//
+// Inline asm support
+//===----------------------------------------------------------------------===//
+TargetLowering::ConstraintType
+XtensaTargetLowering::getConstraintType(StringRef Constraint) const {
+ if (Constraint.size() == 1) {
+ switch (Constraint[0]) {
+ case 'a':
+ case 'd':
+ case 'r':
+ return C_RegisterClass;
+
+ default:
+ break;
+ }
+ }
+ return TargetLowering::getConstraintType(Constraint);
+}
+
+TargetLowering::ConstraintWeight
+XtensaTargetLowering::getSingleConstraintMatchWeight(
+ AsmOperandInfo &info, const char *constraint) const {
+ ConstraintWeight weight = CW_Invalid;
+ Value *CallOperandVal = info.CallOperandVal;
+ // If we don't have a value, we can't do a match,
+ // but allow it at the lowest weight.
+ if (CallOperandVal == NULL)
+ return CW_Default;
+
+ // Look at the constraint type.
+ switch (*constraint) {
+ default:
+ weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+ break;
+
+ case 'a':
+ case 'd':
+ case 'r':
+ if (CallOperandVal->getType()->isIntegerTy())
+ weight = CW_Register;
+ break;
+ }
+ return weight;
+}
+
+std::pair<unsigned, const TargetRegisterClass *>
+XtensaTargetLowering::getRegForInlineAsmConstraint(
+ const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
+ if (Constraint.size() == 1) {
+ // GCC Constraint Letters
+ switch (Constraint[0]) {
+ default:
+ break;
+ case 'a': // Address register
+ case 'd': // Data register (equivalent to 'r')
+ case 'r': // General-purpose register
+ return std::make_pair(0U, &Xtensa::ARRegClass);
+ }
+ }
+ return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
+}
+
+/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+/// vector. If it is invalid, don't add anything to Ops.
+void XtensaTargetLowering::LowerAsmOperandForConstraint(
+ SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+
+ // Only support length 1 constraints for now.
+ if (Constraint.length() > 1)
+ return;
+
+ TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
+}
+
//===----------------------------------------------------------------------===//
// Calling conventions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
index af8cc64b730a..cc811c435c8a 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -82,6 +82,19 @@ public:
/// Returns the size of the platform's va_list object.
unsigned getVaListSizeInBits(const DataLayout &DL) const override;
+ std::pair<unsigned, const TargetRegisterClass *>
+ getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
+ StringRef Constraint, MVT VT) const override;
+ TargetLowering::ConstraintType
+ getConstraintType(StringRef Constraint) const override;
+ TargetLowering::ConstraintWeight
+ getSingleConstraintMatchWeight(AsmOperandInfo &info,
+ const char *constraint) const override;
+
+ void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
+ std::vector<SDValue> &Ops,
+ SelectionDAG &DAG) const override;
+
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool isVarArg,
@@ -138,6 +151,14 @@ private:
// Implement EmitInstrWithCustomInserter for individual operation types.
MachineBasicBlock *emitSelectCC(MachineInstr &MI,
MachineBasicBlock *BB) const;
+
+ unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
+ if (ConstraintCode == "R")
+ return InlineAsm::Constraint_R;
+ else if (ConstraintCode == "ZC")
+ return InlineAsm::Constraint_ZC;
+ return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
+ }
};
} // end namespace llvm
--
2.40.1