0031-Xtensa-Implement-Mul32-Mul32High-and-Div32.patch

From c5fe46bc33a8f1bac150ccc75cb2723094dd8b2e Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov@espressif.com>
Date: Wed, 5 Apr 2023 00:58:50 +0300
Subject: [PATCH 031/158] [Xtensa] Implement Mul32, Mul32High and Div32

 features.
---
 llvm/lib/Target/Xtensa/Xtensa.td              | 15 ++++++++++
 llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 30 ++++++++++++++-----
 llvm/lib/Target/Xtensa/XtensaInstrInfo.td     | 17 +++++++++++
 llvm/lib/Target/Xtensa/XtensaSubtarget.cpp    |  3 ++
 llvm/lib/Target/Xtensa/XtensaSubtarget.h      | 15 ++++++++++
 5 files changed, 73 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
index 4ab0786e16d7..5555d73ca4be 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -52,6 +52,21 @@ def FeatureNSA              : SubtargetFeature<"nsa", "HasNSA", "true",
 def HasNSA                  : Predicate<"Subtarget->hasNSA()">,
                                          AssemblerPredicate<(all_of FeatureNSA)>;
 
+def FeatureMul32            : SubtargetFeature<"mul32", "HasMul32", "true",
+                                               "Enable Xtensa Mul32 option">;
+def HasMul32                : Predicate<"Subtarget->hasMul32()">,
+                                         AssemblerPredicate<(all_of FeatureMul32)>;
+
+def FeatureMul32High        : SubtargetFeature<"mul32high", "HasMul32High", "true",
+                                               "Enable Xtensa Mul32High option">;
+def HasMul32High            : Predicate<"Subtarget->hasMul32High()">,
+                                         AssemblerPredicate<(all_of FeatureMul32High)>;
+
+def FeatureDiv32            : SubtargetFeature<"div32", "HasDiv32", "true",
+                                               "Enable Xtensa Div32 option">;
+def HasDiv32                : Predicate<"Subtarget->hasDiv32()">,
+                                         AssemblerPredicate<(all_of FeatureDiv32)>;
+
 //===----------------------------------------------------------------------===//
 // Xtensa supported processors.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index c70d2045c44d..fc222f47b81b 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -140,17 +140,33 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
     }
   }
 
-  setOperationAction(ISD::MUL, MVT::i32, Expand);
-  setOperationAction(ISD::MULHU, MVT::i32, Expand);
-  setOperationAction(ISD::MULHS, MVT::i32, Expand);
+  if (Subtarget.hasMul32())
+    setOperationAction(ISD::MUL, MVT::i32, Legal);
+  else
+    setOperationAction(ISD::MUL, MVT::i32, Expand);
+
+  if (Subtarget.hasMul32High()) {
+    setOperationAction(ISD::MULHU, MVT::i32, Legal);
+    setOperationAction(ISD::MULHS, MVT::i32, Legal);
+  } else {
+    setOperationAction(ISD::MULHU, MVT::i32, Expand);
+    setOperationAction(ISD::MULHS, MVT::i32, Expand);
+  }
   setOperationAction(ISD::MUL, MVT::i64, Expand);
   setOperationAction(ISD::MULHS, MVT::i64, Expand);
   setOperationAction(ISD::MULHU, MVT::i64, Expand);
 
-  setOperationAction(ISD::SDIV, MVT::i32, Expand);
-  setOperationAction(ISD::UDIV, MVT::i32, Expand);
-  setOperationAction(ISD::SREM, MVT::i32, Expand);
-  setOperationAction(ISD::UREM, MVT::i32, Expand);
+  if (Subtarget.hasDiv32()) {
+    setOperationAction(ISD::SDIV, MVT::i32, Legal);
+    setOperationAction(ISD::UDIV, MVT::i32, Legal);
+    setOperationAction(ISD::SREM, MVT::i32, Legal);
+    setOperationAction(ISD::UREM, MVT::i32, Legal);
+  } else {
+    setOperationAction(ISD::SDIV, MVT::i32, Expand);
+    setOperationAction(ISD::UDIV, MVT::i32, Expand);
+    setOperationAction(ISD::SREM, MVT::i32, Expand);
+    setOperationAction(ISD::UREM, MVT::i32, Expand);
+  }
 
   setOperationAction(ISD::SDIV, MVT::i64, Expand);
   setOperationAction(ISD::UDIV, MVT::i64, Expand);
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index 840b34c621c0..e12f4a632d10 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -1173,3 +1173,20 @@ def NSAU : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s),
                    "nsau\t$t, $s", []>, Requires<[HasNSA]> {
   let r = 0xF;
 }
+
+//===----------------------------------------------------------------------===//
+// Mul32 Instructions
+//===----------------------------------------------------------------------===//
+
+def MULL  : ArithLogic_RRR<0x08, 0x02, "mull", mul, 1>, Requires<[HasMul32]>;
+def MULUH : ArithLogic_RRR<0x0A, 0x02, "muluh", mulhu, 1>, Requires<[HasMul32High]>;
+def MULSH : ArithLogic_RRR<0x0B, 0x02, "mulsh", mulhs, 1>, Requires<[HasMul32High]>;
+
+//===----------------------------------------------------------------------===//
+// Div32 Instructions
+//===----------------------------------------------------------------------===//
+
+def QUOS : ArithLogic_RRR<0x0D, 0x02, "quos", sdiv>, Requires<[HasDiv32]>;
+def QUOU : ArithLogic_RRR<0x0C, 0x02, "quou", udiv>, Requires<[HasDiv32]>;
+def REMS : ArithLogic_RRR<0x0F, 0x02, "rems", srem>, Requires<[HasDiv32]>;
+def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>, Requires<[HasDiv32]>;
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
index d6cc451e0268..03fd8cb99cb9 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
@@ -39,6 +39,9 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   HasLoop = false;
   HasSEXT = false;
   HasNSA = false;
+  HasMul32 = false;
+  HasMul32High = false;
+  HasDiv32 = false;
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, CPUName, FS);
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index ba619caffc0f..f129ddbdb893 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -59,6 +59,15 @@ private:
   // Enable Xtensa NSA option
   bool HasNSA;
 
+  // Enable Xtensa Mul32 option
+  bool HasMul32;
+
+  // Enable Xtensa Mul32High option
+  bool HasMul32High;
+
+  // Enable Xtensa Div32 option
+  bool HasDiv32;
+
   XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
 public:
@@ -90,6 +99,12 @@ public:
 
   bool hasNSA() const { return HasNSA; }
 
+  bool hasMul32() const { return HasMul32; }
+
+  bool hasMul32High() const { return HasMul32High; }
+
+  bool hasDiv32() const { return HasDiv32; }
+
   // Automatically generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 };
-- 
2.40.1