Rewrite - Project

[rodrigomelo9]

• New __init__:

tool = TOOLNAME
project = PROJNAME
outdir = DIRPATH
meta = {
  part: PARTNAME,
  files: [
    {path: FILEPATH, type: FILETYPE, library: LIBNAME, options: OPTIONS},
    {path: FILEPATH, type: FILETYPE, library: LIBNAME, options: OPTIONS},
    {path: FILEPATH, type: FILETYPE, library: LIBNAME, options: OPTIONS}
  ],
  top: TOPNAME,
  params: [
    {name: PARAMNAME, value: PARAMVALUE},
    {name: PARAMNAME, value: PARAMVALUE}
  ],
  vlog_includes: [PATH1, PATH2, PATH3],
  vlog_defines: [
    {name: DEFINENAME, value: DEFINEVALUE},
    {name: DEFINENAME, value: DEFINEVALUE}
  ],
  vhdl_arch: ARCHNAME,
  hooks: {
    prefile: [CMMD1, CMMD2],
    project: [CMMD1, CMMD2],
    preflow: [CMMD1, CMMD2],
    postsyn: [CMMD1, CMMD2],
    postpar: [CMMD1, CMMD2],
    postbit: [CMMD1, CMMD2]
  }
  options: OPTIONS
}

• Change openflow to yosys-nextpnr
• Remove set_outdir
• Move set_param to add_param
• Move add_path to add_vlog_include
• Add add_vlog_define
• Add set_vhdl_arch
• Change imp to par
• Change generate to make
• Change transfer to prog, which only will support fpga (bitstream and position are the only options)
• Remove set_bitstream (absorbed by prog)