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st1vafe6ax_reg.h
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st1vafe6ax_reg.h
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/**
******************************************************************************
* @file st1vafe6ax_reg.h
* @author Sensors Software Solution Team
* @brief This file contains all the functions prototypes for the
* st1vafe6ax_reg.c driver.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2024 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef ST1VAFE6AX_REGS_H
#define ST1VAFE6AX_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
#include <stddef.h>
#include <math.h>
/** @addtogroup ST1VAFE6AX
* @{
*
*/
/** @defgroup Endianness definitions
* @{
*
*/
#ifndef DRV_BYTE_ORDER
#ifndef __BYTE_ORDER__
#define DRV_LITTLE_ENDIAN 1234
#define DRV_BIG_ENDIAN 4321
/** if _BYTE_ORDER is not defined, choose the endianness of your architecture
* by uncommenting the define which fits your platform endianness
*/
//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN
#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN
#else /* defined __BYTE_ORDER__ */
#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__
#define DRV_BYTE_ORDER __BYTE_ORDER__
#endif /* __BYTE_ORDER__*/
#endif /* DRV_BYTE_ORDER */
/**
* @}
*
*/
/** @defgroup STMicroelectronics sensors common types
* @{
*
*/
#ifndef MEMS_SHARED_TYPES
#define MEMS_SHARED_TYPES
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bit0 : 1;
uint8_t bit1 : 1;
uint8_t bit2 : 1;
uint8_t bit3 : 1;
uint8_t bit4 : 1;
uint8_t bit5 : 1;
uint8_t bit6 : 1;
uint8_t bit7 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t bit7 : 1;
uint8_t bit6 : 1;
uint8_t bit5 : 1;
uint8_t bit4 : 1;
uint8_t bit3 : 1;
uint8_t bit2 : 1;
uint8_t bit1 : 1;
uint8_t bit0 : 1;
#endif /* DRV_BYTE_ORDER */
} bitwise_t;
#define PROPERTY_DISABLE (0U)
#define PROPERTY_ENABLE (1U)
/** @addtogroup Interfaces_Functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
* MANDATORY: return 0 -> no Error.
* @{
*
*/
typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
typedef void (*stmdev_mdelay_ptr)(uint32_t millisec);
typedef struct
{
/** Component mandatory fields **/
stmdev_write_ptr write_reg;
stmdev_read_ptr read_reg;
/** Component optional fields **/
stmdev_mdelay_ptr mdelay;
/** Customizable optional pointer **/
void *handle;
} stmdev_ctx_t;
/**
* @}
*
*/
#endif /* MEMS_SHARED_TYPES */
#ifndef MEMS_UCF_SHARED_TYPES
#define MEMS_UCF_SHARED_TYPES
/** @defgroup Generic address-data structure definition
* @brief This structure is useful to load a predefined configuration
* of a sensor.
* You can create a sensor configuration by your own or using
* Unico / Unicleo tools available on STMicroelectronics
* web site.
*
* @{
*
*/
typedef struct
{
uint8_t address;
uint8_t data;
} ucf_line_t;
/**
* @}
*
*/
#endif /* MEMS_UCF_SHARED_TYPES */
/**
* @}
*
*/
/** @defgroup ST1VAFE6AX_Infos
* @{
*
*/
/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/
#define ST1VAFE6AX_I2C_ADD_L 0xD5U
#define ST1VAFE6AX_I2C_ADD_H 0xD7U
/** Device Identification (Who am I) **/
#define ST1VAFE6AX_ID 0x71U
/**
* @}
*
*/
/** @defgroup bitfields page main
* @{
*
*/
#define ST1VAFE6AX_FUNC_CFG_ACCESS 0x1U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 2;
uint8_t sw_por : 1;
uint8_t fsm_wr_ctrl_en : 1;
uint8_t not_used1 : 3;
uint8_t emb_func_reg_access : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t emb_func_reg_access : 1;
uint8_t not_used1 : 3;
uint8_t fsm_wr_ctrl_en : 1;
uint8_t sw_por : 1;
uint8_t not_used0 : 2;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_func_cfg_access_t;
#define ST1VAFE6AX_PIN_CTRL 0x2U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 5;
uint8_t ibhr_por_en : 1;
uint8_t sdo_pu_en : 1;
uint8_t not_used1 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used1 : 1;
uint8_t sdo_pu_en : 1;
uint8_t ibhr_por_en : 1;
uint8_t not_used0 : 5;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_pin_ctrl_t;
#define ST1VAFE6AX_IF_CFG 0x3U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t i2c_i3c_disable : 1;
uint8_t not_used0 : 1;
uint8_t sim : 1;
uint8_t pp_od : 1;
uint8_t h_lactive : 1;
uint8_t asf_ctrl : 1;
uint8_t not_used1 : 1;
uint8_t sda_pu_en : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t sda_pu_en : 1;
uint8_t not_used1 : 1;
uint8_t asf_ctrl : 1;
uint8_t h_lactive : 1;
uint8_t pp_od : 1;
uint8_t sim : 1;
uint8_t not_used0 : 1;
uint8_t i2c_i3c_disable : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_if_cfg_t;
#define ST1VAFE6AX_FIFO_CTRL1 0x7U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t wtm : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t wtm : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_fifo_ctrl1_t;
#define ST1VAFE6AX_FIFO_CTRL2 0x8U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xl_dualc_batch_from_fsm : 1;
uint8_t uncompr_rate : 2;
uint8_t not_used0 : 1;
uint8_t odr_chg_en : 1;
uint8_t not_used1 : 1;
uint8_t fifo_compr_rt_en : 1;
uint8_t stop_on_wtm : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t stop_on_wtm : 1;
uint8_t fifo_compr_rt_en : 1;
uint8_t not_used1 : 1;
uint8_t odr_chg_en : 1;
uint8_t not_used0 : 1;
uint8_t uncompr_rate : 2;
uint8_t xl_dualc_batch_from_fsm : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_fifo_ctrl2_t;
#define ST1VAFE6AX_FIFO_CTRL3 0x9U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t bdr_xl : 4;
uint8_t bdr_gy : 4;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t bdr_gy : 4;
uint8_t bdr_xl : 4;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_fifo_ctrl3_t;
#define ST1VAFE6AX_FIFO_CTRL4 0x0AU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fifo_mode : 3;
uint8_t not_used0 : 1;
uint8_t odr_t_batch : 2;
uint8_t dec_ts_batch : 2;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t dec_ts_batch : 2;
uint8_t odr_t_batch : 2;
uint8_t not_used0 : 1;
uint8_t fifo_mode : 3;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_fifo_ctrl4_t;
#define ST1VAFE6AX_COUNTER_BDR_REG1 0x0BU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 2;
uint8_t ah_bio_batch_en : 1;
uint8_t not_used0 : 2;
uint8_t trig_counter_bdr : 2;
uint8_t not_used1 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used1 : 1;
uint8_t trig_counter_bdr : 2;
uint8_t not_used0 : 2;
uint8_t ah_bio_batch_en : 1;
uint8_t cnt_bdr_th : 2;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_counter_bdr_reg1_t;
#define ST1VAFE6AX_COUNTER_BDR_REG2 0x0CU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t cnt_bdr_th : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t cnt_bdr_th : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_counter_bdr_reg2_t;
#define ST1VAFE6AX_INT1_CTRL 0x0DU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int1_drdy_xl : 1;
uint8_t int1_drdy_g : 1;
uint8_t not_used0 : 1;
uint8_t int1_fifo_th : 1;
uint8_t int1_fifo_ovr : 1;
uint8_t int1_fifo_full : 1;
uint8_t int1_cnt_bdr : 1;
uint8_t not_used1 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used1 : 1;
uint8_t int1_cnt_bdr : 1;
uint8_t int1_fifo_full : 1;
uint8_t int1_fifo_ovr : 1;
uint8_t int1_fifo_th : 1;
uint8_t not_used0 : 1;
uint8_t int1_drdy_g : 1;
uint8_t int1_drdy_xl : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_int1_ctrl_t;
#define ST1VAFE6AX_INT2_CTRL 0x0EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int2_drdy_xl : 1;
uint8_t int2_drdy_g : 1;
uint8_t not_used0 : 1;
uint8_t int2_fifo_th : 1;
uint8_t int2_fifo_ovr : 1;
uint8_t int2_fifo_full : 1;
uint8_t int2_cnt_bdr : 1;
uint8_t int2_emb_func_endop : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t int2_emb_func_endop : 1;
uint8_t int2_cnt_bdr : 1;
uint8_t int2_fifo_full : 1;
uint8_t int2_fifo_ovr : 1;
uint8_t int2_fifo_th : 1;
uint8_t not_used0 : 1;
uint8_t int2_drdy_g : 1;
uint8_t int2_drdy_xl : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_int2_ctrl_t;
#define ST1VAFE6AX_WHO_AM_I 0x0FU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t id : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t id : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_who_am_i_t;
#define ST1VAFE6AX_CTRL1 0x10U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t odr_xl : 4;
uint8_t op_mode_xl : 3;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t op_mode_xl : 3;
uint8_t odr_xl : 4;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl1_t;
#define ST1VAFE6AX_CTRL2 0x11U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t odr_g : 4;
uint8_t op_mode_g : 3;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t op_mode_g : 3;
uint8_t odr_g : 4;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl2_t;
#define ST1VAFE6AX_CTRL3 0x12U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t sw_reset : 1;
uint8_t not_used0 : 1;
uint8_t if_inc : 1;
uint8_t not_used1 : 3;
uint8_t bdu : 1;
uint8_t boot : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t boot : 1;
uint8_t bdu : 1;
uint8_t not_used1 : 3;
uint8_t if_inc : 1;
uint8_t not_used0 : 1;
uint8_t sw_reset : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl3_t;
#define ST1VAFE6AX_CTRL4 0x13U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used1 : 1;
uint8_t drdy_pulsed : 1;
uint8_t int2_drdy_temp : 1;
uint8_t drdy_mask : 1;
uint8_t int2_on_int1 : 1;
uint8_t not_used0 : 3;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 3;
uint8_t int2_on_int1 : 1;
uint8_t drdy_mask : 1;
uint8_t int2_drdy_temp : 1;
uint8_t drdy_pulsed : 1;
uint8_t not_used1 : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl4_t;
#define ST1VAFE6AX_CTRL5 0x14U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t int_en_i3c : 1;
uint8_t bus_act_sel : 2;
uint8_t not_used0 : 5;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 5;
uint8_t bus_act_sel : 2;
uint8_t int_en_i3c : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl5_t;
#define ST1VAFE6AX_CTRL6 0x15U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fs_g : 4;
uint8_t lpf1_g_bw : 3;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t lpf1_g_bw : 3;
uint8_t fs_g : 4;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl6_t;
#define ST1VAFE6AX_CTRL7 0x16U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t lpf1_g_en : 1;
uint8_t not_used0 : 1;
uint8_t ah_bio2_en : 1;
uint8_t ah_bio1_en : 1;
uint8_t ah_bio_c_zin : 2;
uint8_t int2_drdy_ah_bio : 1;
uint8_t ah_bio_en : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ah_bio_en : 1;
uint8_t int2_drdy_ah_bio : 1;
uint8_t ah_bio_c_zin : 2;
uint8_t ah_bio1_en : 1;
uint8_t ah_bio2_en : 1;
uint8_t not_used0 : 1;
uint8_t lpf1_g_en : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl7_t;
#define ST1VAFE6AX_CTRL8 0x17U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t fs_xl : 2;
uint8_t not_used0 : 1;
uint8_t xl_dualc_en : 1;
uint8_t ah_bio_hpf : 1;
uint8_t hp_lpf2_xl_bw : 3;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t hp_lpf2_xl_bw : 3;
uint8_t ah_bio_hpf : 1;
uint8_t xl_dualc_en : 1;
uint8_t not_used0 : 1;
uint8_t fs_xl : 2;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl8_t;
#define ST1VAFE6AX_CTRL9 0x18U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t usr_off_on_out : 1;
uint8_t usr_off_w : 1;
uint8_t not_used0 : 1;
uint8_t lpf2_xl_en : 1;
uint8_t hp_slope_xl_en : 1;
uint8_t xl_fastsettl_mode : 1;
uint8_t hp_ref_mode_xl : 1;
uint8_t ah_bio_lpf : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ah_bio_lpf : 1;
uint8_t hp_ref_mode_xl : 1;
uint8_t xl_fastsettl_mode : 1;
uint8_t hp_slope_xl_en : 1;
uint8_t lpf2_xl_en : 1;
uint8_t not_used0 : 1;
uint8_t usr_off_w : 1;
uint8_t usr_off_on_out : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl9_t;
#define ST1VAFE6AX_CTRL10 0x19U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t st_xl : 2;
uint8_t st_g : 2;
uint8_t xl_st_offset : 1;
uint8_t ah_bio_sw : 1;
uint8_t emb_func_debug : 1;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t emb_func_debug : 1;
uint8_t ah_bio_sw : 1;
uint8_t xl_st_offset : 1;
uint8_t st_g : 2;
uint8_t st_xl : 2;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl10_t;
#define ST1VAFE6AX_CTRL_STATUS 0x1AU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 2;
uint8_t fsm_wr_ctrl_status : 1;
uint8_t not_used1 : 5;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used1 : 5;
uint8_t fsm_wr_ctrl_status : 1;
uint8_t not_used0 : 2;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ctrl_status_t;
#define ST1VAFE6AX_FIFO_STATUS1 0x1BU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t diff_fifo : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_fifo_status1_t;
#define ST1VAFE6AX_FIFO_STATUS2 0x1CU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t diff_fifo : 1;
uint8_t not_used0 : 2;
uint8_t fifo_ovr_latched : 1;
uint8_t counter_bdr_ia : 1;
uint8_t fifo_full_ia : 1;
uint8_t fifo_ovr_ia : 1;
uint8_t fifo_wtm_ia : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t fifo_wtm_ia : 1;
uint8_t fifo_ovr_ia : 1;
uint8_t fifo_full_ia : 1;
uint8_t counter_bdr_ia : 1;
uint8_t fifo_ovr_latched : 1;
uint8_t not_used0 : 2;
uint8_t diff_fifo : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_fifo_status2_t;
#define ST1VAFE6AX_ALL_INT_SRC 0x1DU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ff_ia : 1;
uint8_t wu_ia : 1;
uint8_t tap_ia : 1;
uint8_t not_used0 : 1;
uint8_t d6d_ia : 1;
uint8_t sleep_change_ia : 1;
uint8_t not_used1 : 1;
uint8_t emb_func_ia : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t emb_func_ia : 1;
uint8_t not_used1 : 1;
uint8_t sleep_change_ia : 1;
uint8_t d6d_ia : 1;
uint8_t not_used0 : 1;
uint8_t tap_ia : 1;
uint8_t wu_ia : 1;
uint8_t ff_ia : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_all_int_src_t;
#define ST1VAFE6AX_STATUS_REG 0x1EU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t xlda : 1;
uint8_t gda : 1;
uint8_t tda : 1;
uint8_t ah_bioda : 1;
uint8_t not_used0 : 3;
uint8_t timestamp_endcount : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t timestamp_endcount : 1;
uint8_t not_used0 : 3;
uint8_t ah_bioda : 1;
uint8_t tda : 1;
uint8_t gda : 1;
uint8_t xlda : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_status_reg_t;
#define ST1VAFE6AX_OUT_TEMP_L 0x20U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t temp : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t temp : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_out_temp_l_t;
#define ST1VAFE6AX_OUT_TEMP_H 0x21U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t temp : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t temp : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_out_temp_h_t;
#define ST1VAFE6AX_OUTX_L_G 0x22U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outx_g : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outx_g : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outx_l_g_t;
#define ST1VAFE6AX_OUTX_H_G 0x23U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outx_g : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outx_g : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outx_h_g_t;
#define ST1VAFE6AX_OUTY_L_G 0x24U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outy_g : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outy_g : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outy_l_g_t;
#define ST1VAFE6AX_OUTY_H_G 0x25U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outy_g : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outy_g : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outy_h_g_t;
#define ST1VAFE6AX_OUTZ_L_G 0x26U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outz_g : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outz_g : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outz_l_g_t;
#define ST1VAFE6AX_OUTZ_H_G 0x27U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outz_g : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outz_g : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outz_h_g_t;
#define ST1VAFE6AX_OUTZ_L_A 0x28U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outz_a : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outz_a : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outz_l_a_t;
#define ST1VAFE6AX_OUTZ_H_A 0x29U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outz_a : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outz_a : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outz_h_a_t;
#define ST1VAFE6AX_OUTY_L_A 0x2AU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outy_a : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outy_a : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outy_l_a_t;
#define ST1VAFE6AX_OUTY_H_A 0x2BU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outy_a : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outy_a : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outy_h_a_t;
#define ST1VAFE6AX_OUTX_L_A 0x2CU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outx_a : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outx_a : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outx_l_a_t;
#define ST1VAFE6AX_OUTX_H_A 0x2DU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t outx_a : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t outx_a : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_outx_h_a_t;
#define ST1VAFE6AX_UI_OUTZ_L_A_DUALC 0x34U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ui_outz_a_dualc : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ui_outz_a_dualc : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ui_outz_l_a_dualc_t;
#define ST1VAFE6AX_UI_OUTZ_H_A_DUALC 0x35U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ui_outz_a_dualc : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ui_outz_a_dualc : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ui_outz_h_a_dualc_t;
#define ST1VAFE6AX_UI_OUTY_L_A_DUALC 0x36U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ui_outy_a_dualc : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ui_outy_a_dualc : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ui_outy_l_a_dualc_t;
#define ST1VAFE6AX_UI_OUTY_H_A_DUALC 0x37U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ui_outy_a_dualc : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ui_outy_a_dualc : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ui_outy_h_a_dualc_t;
#define ST1VAFE6AX_UI_OUTX_L_A_DUALC 0x38U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ui_outx_a_dualc : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ui_outx_a_dualc : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ui_outx_l_a_dualc_t;
#define ST1VAFE6AX_UI_OUTX_H_A_DUALC 0x39U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ui_outx_a_dualc : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ui_outx_a_dualc : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ui_outx_h_a_dualc_t;
#define ST1VAFE6AX_AH_BIO_OUT_L 0x3AU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ah_bio : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ah_bio : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ah_bio_out_l_t;
#define ST1VAFE6AX_AH_BIO_OUT_H 0x3BU
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t ah_bio : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t ah_bio : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_ah_bio_out_h_t;
#define ST1VAFE6AX_TIMESTAMP0 0x40U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t timestamp : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t timestamp : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_timestamp0_t;
#define ST1VAFE6AX_TIMESTAMP1 0x41U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t timestamp : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t timestamp : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_timestamp1_t;
#define ST1VAFE6AX_TIMESTAMP2 0x42U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t timestamp : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t timestamp : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_timestamp2_t;
#define ST1VAFE6AX_TIMESTAMP3 0x43U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t timestamp : 8;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t timestamp : 8;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_timestamp3_t;
#define ST1VAFE6AX_WAKE_UP_SRC 0x45U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t x_wu : 1;
uint8_t y_wu : 1;
uint8_t z_wu : 1;
uint8_t wu_ia : 1;
uint8_t sleep_state : 1;
uint8_t ff_ia : 1;
uint8_t sleep_change_ia : 1;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t sleep_change_ia : 1;
uint8_t ff_ia : 1;
uint8_t sleep_state : 1;
uint8_t wu_ia : 1;
uint8_t z_wu : 1;
uint8_t y_wu : 1;
uint8_t x_wu : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_wake_up_src_t;
#define ST1VAFE6AX_TAP_SRC 0x46U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t x_tap : 1;
uint8_t y_tap : 1;
uint8_t z_tap : 1;
uint8_t tap_sign : 1;
uint8_t not_used0 : 1;
uint8_t double_tap : 1;
uint8_t single_tap : 1;
uint8_t tap_ia : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t tap_ia : 1;
uint8_t single_tap : 1;
uint8_t double_tap : 1;
uint8_t not_used0 : 1;
uint8_t tap_sign : 1;
uint8_t z_tap : 1;
uint8_t y_tap : 1;
uint8_t x_tap : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_tap_src_t;
#define ST1VAFE6AX_D6D_SRC 0x47U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t zl : 1;
uint8_t zh : 1;
uint8_t yl : 1;
uint8_t yh : 1;
uint8_t xl : 1;
uint8_t xh : 1;
uint8_t d6d_ia : 1;
uint8_t not_used0 : 1;
#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
uint8_t not_used0 : 1;
uint8_t d6d_ia : 1;
uint8_t xh : 1;
uint8_t xl : 1;
uint8_t yh : 1;
uint8_t yl : 1;
uint8_t zh : 1;
uint8_t zl : 1;
#endif /* DRV_BYTE_ORDER */
} st1vafe6ax_d6d_src_t;
#define ST1VAFE6AX_EMB_FUNC_STATUS_MAINPAGE 0x49U
typedef struct
{
#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
uint8_t not_used0 : 3;
uint8_t is_step_det : 1;
uint8_t is_tilt : 1;