Can't infer width of Payload #1404
Comments
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In a similar fashion.. why do none of these work? case class BoolPayload() extends Area {
val BOOL_PAYLOAD = Payload(Bool())
val a = BOOL_PAYLOAD ? B"1" | B"0"
val b = (BOOL_PAYLOAD === True) ? B"1" | B"0"
val c = (B(BOOL_PAYLOAD) === B"1") ? B"1" | B"0"
val d = (BOOL_PAYLOAD.asBits === B"1") ? B"1" | B"0"
val e = Bits(1 bit)
when(BOOL_PAYLOAD) {
e := B"1"
}.otherwise {
e := B"0"
}
} |
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Hi, Sometime, scala has some limitation / restrictions with the range of implicits and need a bit of help XD Here is one workaround : Another one :
I tried, but can't reproduce that issue, it may be related to something else ? Also i just tried : val decode = CtrlLink()
val BOOL_PAYLOAD = Payload(Bool())
val decoder = new decode.Area {
val a = BOOL_PAYLOAD ? B"1" | B"0"
val b = (BOOL_PAYLOAD === True) ? B"1" | B"0"
val c = (B(BOOL_PAYLOAD) === B"1") ? B"1" | B"0"
val d = (BOOL_PAYLOAD.asBits === B"1") ? B"1" | B"0"
val e = Bits(1 bit)
when(BOOL_PAYLOAD) {
e := B"1"
}.otherwise {
e := B"0"
}
}
Builder(decode)They all work for me In your example i think the issue is that you aren't in a "Node" context (new decode.Area) So, the pipeline API has no "Node" to extract the payload from.
<3 Pain pain pain <3 |
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Hi there @Dolu1990 package curlyrv
import spinal.core._
import spinal.lib._
import spinal.lib.misc.pipeline._
import scala.collection.mutable.ArrayBuffer
case class Pipes() extends Area {
val decode = CtrlLink()
val IR = Payload(Bits(32 bits))
val OPCODE = Payload(Bits(7 bits))
val RD = Payload(UInt(5 bits))
Builder(decode)
}
case class DecodeOps(pipes: Pipes) {
import pipes._
val decoder = new decode.Area {
OPCODE := IR(6 downto 0)
RD := U(IR(11 downto 7))
}
}
case class Bug() extends Component {
val pipes = Pipes()
val decodeOps = DecodeOps(pipes)
}
object BugTop extends App {
Config.spinal.generateVhdl(Bug()).printPruned()
}The compile fails with error What am I missing? Full output of `sbt runMain curlyrv.BugTop` |
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BTW if I rewrite it as: val ir = U(IR)
RD := ir(11 downto 7)The error becomes:
Full output of `sbt runMain curlyrv.BugTop` |
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@NikLeberg After fixing that we have to also connect inputs/outputs, otherwise all the HW gets optimized away and we might miss some issues. It works as expected like this (just a quick fix, not "nice" code): case class Pipes() extends Area {
val decode = CtrlLink()
val IR = Payload(Bits(32 bits))
val OPCODE = Payload(Bits(7 bits))
val RD = Payload(UInt(4 bits))
}
case class DecodeOps(pipes: Pipes) {
import pipes._
val decoder = new decode.Area {
OPCODE := IR(6 downto 0)
RD := U(IR(10 downto 7))
}
}
case class Bug() extends Component {
val io = new Bundle {
val ir = in port Bits(32 bit)
val rd = out port UInt(4 bits)
val opcode = out port Bits(7 bits)
}
val pipes = Pipes()
val decodeOps = DecodeOps(pipes)
pipes.decode(pipes.IR) := io.ir
io.rd := pipes.decode.down(pipes.RD)
io.opcode := pipes.decode.down(pipes.OPCODE)
Builder(pipes.decode)
}
object BugTop extends App {
SpinalConfig().generateVhdl{Bug()}.printPruned()
}We should have a look whether we can generate a separate error message in this case - the current one is just from the fallout and is an aftereffect. OT: In most cases you should place the |
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Hi, I found one bug in the SpinalHDL library which was preventing width inferation on the very first signal created (if created by the pipelining API) Here is the fix : It may fix your issue aswell. |
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Hi @Dolu1990 Awesome! If I compile my example from above (with the fix of calling Thank you both for your work and suggestions. For me this issue is fixed and I'm closing it. Feel free to reopen if you want to track:
Thanks, Nik |
Hi there!
Amazing project I have to say! Right when VHDL got on my nerves with its verbosity I found this. And the advanced generator functionality is what really drives it home.
Right, so I played around with
Payloadand am trying to build, of course, a RISC-V core with it. Thats when I stumbled over:Where
sbtgives me this:Please tell me if I'm doing something wrong. I expected
OPCODEto be implicitly converted to Bits, but it is not? If i wrap it inB()it works fine.Interestingly if I do
OPCODE.asBitsin a bit less mimized version of my design I get the metals environment to spit out interesting errors:As I'm no expert in Scala, what is happening here?
Thanks!
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