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cuda_kernel_matrix_mult_trans.go
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cuda_kernel_matrix_mult_trans.go
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package mt
const KER_MATRIX_MULT_TRANS = `
//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Thu Mar 13 19:31:35 2014 (1394735495)
// Cuda compilation tools, release 6.0, V6.0.1
//
.version 4.0
.target sm_30
.address_size 64
.visible .entry matrixMulTrans(
.param .u64 matrixMulTrans_param_0,
.param .u64 matrixMulTrans_param_1,
.param .u64 matrixMulTrans_param_2,
.param .u32 matrixMulTrans_param_3,
.param .u32 matrixMulTrans_param_4,
.param .u32 matrixMulTrans_param_5,
.param .u32 matrixMulTrans_param_6,
.param .u32 matrixMulTrans_param_7
)
{
.reg .pred %p<6>;
.reg .s32 %r<23>;
.reg .s64 %rd<19>;
.reg .f64 %fd<10>;
ld.param.u64 %rd7, [matrixMulTrans_param_0];
ld.param.u64 %rd8, [matrixMulTrans_param_1];
ld.param.u64 %rd9, [matrixMulTrans_param_2];
ld.param.u32 %r8, [matrixMulTrans_param_3];
ld.param.u32 %r9, [matrixMulTrans_param_4];
ld.param.u32 %r10, [matrixMulTrans_param_5];
ld.param.u32 %r11, [matrixMulTrans_param_6];
ld.param.u32 %r12, [matrixMulTrans_param_7];
mov.u32 %r1, %ctaid.x;
mov.u32 %r2, %tid.x;
mad.lo.s32 %r13, %r1, %r9, %r2;
mov.u32 %r3, %ctaid.y;
mov.u32 %r4, %tid.y;
mad.lo.s32 %r14, %r3, %r10, %r4;
mad.lo.s32 %r5, %r14, %r11, %r13;
setp.lt.s32 %p1, %r5, %r12;
setp.lt.s32 %p2, %r13, %r11;
and.pred %p3, %p1, %p2;
@!%p3 bra BB0_6;
bra.uni BB0_1;
BB0_1:
setp.gt.s32 %p4, %r8, 0;
@%p4 bra BB0_3;
mov.f64 %fd9, 0d0000000000000000;
bra.uni BB0_5;
BB0_3:
cvta.to.global.u64 %rd10, %rd9;
cvta.to.global.u64 %rd11, %rd8;
mul.lo.s32 %r17, %r8, %r14;
shl.b32 %r18, %r17, 1;
mul.wide.s32 %rd12, %r18, 4;
add.s64 %rd18, %rd11, %rd12;
mul.lo.s32 %r20, %r8, %r13;
shl.b32 %r21, %r20, 1;
mul.wide.s32 %rd13, %r21, 4;
add.s64 %rd17, %rd10, %rd13;
mov.f64 %fd9, 0d0000000000000000;
mov.u32 %r22, 0;
BB0_4:
ld.global.f64 %fd6, [%rd17];
ld.global.f64 %fd7, [%rd18];
mul.rn.f64 %fd8, %fd7, %fd6;
add.rn.f64 %fd9, %fd9, %fd8;
add.s64 %rd18, %rd18, 8;
add.s64 %rd17, %rd17, 8;
add.s32 %r22, %r22, 1;
setp.lt.s32 %p5, %r22, %r8;
@%p5 bra BB0_4;
BB0_5:
cvta.to.global.u64 %rd14, %rd7;
mul.wide.s32 %rd15, %r5, 8;
add.s64 %rd16, %rd14, %rd15;
st.global.f64 [%rd16], %fd9;
BB0_6:
ret;
}
`