Chisel 3.5 Release Candidate 1

[chick]

Release notes for Chisel3 Release 3.5.0-RC1

Feature

• DataView is a mechanism for "viewing" Scala objects as a subtype of Data. Often, this is useful for viewing one subtype of Data, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. (Add DataView #1955)

• Instance/Definition introduces a new experimental API for module instantiation that disentagles elaborating the definition (or implementation) from instantiation of a given module. This solves Chisel's longstanding reliance on "Deduplication" for generating Verilog with multiple instances of the same module. (Instance/Definition (formerly Template) #2045)

• ExtModule now supports built in support for providing (ExtModule's lacked support built in support for providing #1154)

• Naming improvements

  • When prefixing with a data, eagerly get local name (When prefixing with a data, eagerly get local name #1614)
  • Use Data refs for name prefixing with aggregate elements (Use Data refs for name prefixing with aggregate elements #1616)
  • Added Force Name API (Added Force Name API #1634)
  • Bugfix - module name collision for injecting aspect (Bugfix - module name collision for injecting aspect #1635)

• Support VecLiterals, useful as Vec initializers and in unit testing.(Introduce VecLiterals #1834)

• add new APIs to BitPat (Add toString method to BitPat #1819)

  • add Y, N, select, slice, and ## to BitPat.
  • Add toString method to BitPat

• Verification

  • Guard statements with module reset (verification: guard statements with module reset #1891)
  • create and extend annotatable BaseSim class for verification nodes (create and extend annotatable BaseSim class for verification nodes #1968)
  • Make printf return BaseSim subclass so it can be named/annotated (have printf return BaseSim subclass so it can be named/annotated #1992)

• Implement Espresso Decoder (Implement Espresso Decoder #1914)(Espresso Decoder #1964)

• Add when.cond for getting the current when condition (Add when.cond for getting the current when condition #1694)

• add ShiftRegisters to expose register inside ShiftRegister.

• Parametrized Mem- & SyncReadMem-based implementation of the Queue class (Parametrized Mem- & SyncReadMem-based implementation of the Queue class #1740)

• Import memory files inline for Verilog generation (Import memory files inline for Verilog generation #1805)

• allowReflectiveAutoCloneType must work outside of Builder context (allowReflectiveAutoCloneType must work outside of Builder context #1811)

• Make plugin autoclonetype always on (Make plugin autoclonetype always on #1826)

• Add getVerilog in Chisel3 (Verilog #1921)

• Merge minimized table before return as a TruthTable (Merge minimized table before return as a TruthTable #1933)

• Add isOneOf method to ChiselEnum (Add isOneOf method to ChiselEnum #1966)

• Lazy .fir Emission, use BufferedCustomFileEmission in CircuitSerializationAnnotation (Lazy .fir Emission #2083)

API Modification

• Bundles can no longer be instantiated with bound hardware
• Bundles no longer can be instantiated with bound types
• Update core/src/main/scala/chisel3/Aggregate.scala
• deprecate getPorts with modulePorts. (deprecate getPorts with modulePorts. #1945)
• Stop Emitting BlackBoxResourceAnno. This removes the - need for a FIRRTL compiler to grok the Java Resource API in order to handle BlackBoxResourceAnno. (Stop Emitting BlackBoxResourceAnno #1954)
• Added flush capability to Queue (Added flush capability to Queue #2030)
• Added VecInit factory methods (fill,iterate)(Added VecInit factory methods (fill,iterate) #2059)
• Add multiple dimensions to VecInit fill and iterate (Add multiple dimensions to VecInit fill and iterate  #2065)

Fix

• Fix chisel3 <> for Bundles that contain compatibility Bundles (Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) #2031)(FIx firrtl typo in README versioning section #2097)
• Fixing aspect injection context bug (Fixing aspect injection context bug #1874)
• Make it legal for concrete resets to drive abstract reset
• This has been legal in FIRRTL since v1.2.3 (Make it legal for concrete resets to drive abstract reset #2018)
• Fix chisel3 <> for Bundles that contain compatibility Bundles.
• BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a
• Bundle defined in import Chisel._. (Fix chisel3 <> for Bundles that contain compatibility Bundles #2023)
• Fix higher-kinded types for autoclonetype (Fix higher-kinded types for autoclonetype #2121)
• Fix bug where refs may not get set for Records (Fix bug where refs may not get set for Records #1645)
• SeqUtils asUInt endian-ness: hi/lo instead of right/left (SeqUtils asUInt endian-ness: hi/lo instead of right/left #1647)
• Bugfix - adding external modules was broken (Bugfix - adding external modules was broken (bug introduced in #1635) #1649)
• Improve source locators for switch statements. (Improve source locators for switch statements. #1669)
• Fix RegInit of Bundle lits (Fix RegInit of Bundle lits #1688)
• Fix incorrect usage of emitFirrtl in test (Fix incorrect usage of emitFirrtl in test #1817)
• Don't toggle top.cpp clock and reset on same cycle (Don't toggle top.cpp clock and reset on same cycle #1820)
• Fix ShiftRegister with 0 delay. (Fix ShiftRegister with 0 delay.  #1903)
• implement model checking API for chiseltest (Implement PLA #1912)
• Fix CloneModuleAsRecord support for .toTarget (Fix CloneModuleAsRecord support for .toTarget #1974)
• Fix aop.Select behavior for CloneModuleAsRecord (Fix aop.Select behavior for CloneModuleAsRecord #1993)
• Fix ChiselEnum warnings and use Logger for warnings instead of println (Fix ChiselEnum warnings and use Logger for warnings instead of println #1999)
• Fix a bug causes incorrect pla generation when input is ?(Fix a bug causes incorrect pla generation when input is ? #2113)

Documentation

• MovingAverage3 => MovingSum3, The example in the README is a sum, not an average. (MovingAverage3 => MovingSum3 #2050)
• Fix broken mdoc (Fix broken mdoc #1600)
• Move more docs (Move more docs #1601)
• Move Chisel3 to SPDX license conventions (Move Chisel3 to SPDX license conventions #1604)
• Small changes to memory doc (Small changes to memory doc #2062)
• Fixed broken link to type hierarchy diagram (Fixed broken link to type hierarchy diagram #1611)
• Delete index.md (Delete index.md #1613)
• Fix crosslinks in mdoc. Can't use md suffix (Fix crosslinks in mdoc. Can't use md suffix #1640)
• Fix broken links in docs (Fix broken links in docs #1643)
• Ignore tests using System.setSecurityManager (Ignore tests using System.setSecurityManager #1661)
• Update some README links to chipsalliance (Update some README links to chipsalliance #1673)
• readme: simplify sbt snippet and update to the latest stable release (readme: simplify sbt snippet and update to the latest stable release #1686)
• Adding ChiselEnum Documentation Entry (Adding ChiselEnum Documentation Entry #1795)
• Minor docs improvements (Minor docs improvements #1774)
• Reorganize website docs (Reorganize website docs #1806)
• Update the FAQ and add doc on versioning (Update the FAQ and add doc on versioning #1827)
• Provide useful message on Vec.apply require (Provide useful message on Vec.apply require #1838)
• Fix formatting issue of links (Fix formatting issue of links #1844)
• Fix Gitter chat room link (Fix Gitter chat room link #1848)
• Add documentation guide about memory initialization (Add documentation guide about memory initialization #1850)
• Add "how to tie off to 0" to the Cookbook (Add "how to tie off to 0" to the Cookbook #1857)
• Add a link to the Chisel book (Add a link to the Chisel book #1872)
• Update type_hierarchy (Add link to Chisel Breakdown slides to README #1979)
• Add example of stripping directions from type ([docs] Add example of stripping directions from type #2074)

Testing and Continuous Integration

• Use requireIsChiselType check on Bundle elements
• Merge branch 'master' into autoclonetype2-bug-fixes
• Add bundle test for recursively bound aggregates (Bundles can no longer be instantiated with bound hardware #2046)
• Switch to using Github Actions CI (Switch to using Github Actions CI #1690)
• Add seven segment display decoder test case (Add seven segment display decoder test case #1972)

Deprecations and other removals

• Remove Deprecated APIs (Remove deprecations  #1730)
• remove 2.11 dedicated code. (remove 2.11 dedicated code. #1744)
• 8a73362 Remove val io
• 7e4d1ee Update docs for the removal of val io and MultiIOModule
• 6c6ec71 Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModule

Miscellany

• Also add newline to end of verilog modifier code blocks so that there is always a newline between code blocks and following material. (Fix ChiselEnum docs #2016)
• Change prefix stack to List[String] (Change prefix stack to List[String] #1617)
• Provide user source locators in Builder.error errors (Provide user source locators in Builder.error errors #1618)
• Enable Cat of Zero Element Vec (Enable Cat of Zero Element Vec #1623)
• Make -e option work with ChiselStage methods (Make -e option work with ChiselStage methods #1630)
• Remove Data.setRef assertion (Remove Data.setRef assertion #1654)
• For HasId.setRef, have first set win (with force override) (For HasId.setRef, have first set win (with force override) #1655)
• Refine autonaming to have more intuitive behavior (Refine autonaming to have more intuitive behavior #1660)
• Add custom mdoc modifier for emitted Verilog (Add custom mdoc modifier for emitted Verilog #1666)
• (encore) Builder: use LazyLogging.logger.warn to print elaboration message ((encore) Builder: use LazyLogging.logger.warn to print elaboration message #1670)
• 3bea616 [plugin] Disable BundleComponent by default, add option to enable
• a8d3238 [plugin] Stop autoclonetype stack traces when using plugin
• 1494231 [plugin] Implement autoclonetype in the compiler plugin
• e80e9a3 [plugin] Split ChiselComponent into its own file
• 0a0d7c6 Make it possible to GC Data instances
• 53b6204 Add no-plugin-tests for testing Chisel without the compiler plugin
• add helper function to convert chirrtl to firrtl. (add helper function to convert chirrtl to firrtl. #1854)
• b88ae1f Deprecate override_clock and override_reset in Module
• 5ece5aa Rename MultiIOModule to Module
• b96e7dd farewell Scala 2.11
• use Seq.iter for oneline implementation. (add ShiftRegisters to expose register inside ShiftRegister. #1723)
• Expose AnnotationSeq to Module. (Expose AnnotationSeq to Module. #1731)
• Fix Mergify condition for labeling backports (Fix Mergify condition for labeling backports #1742)
• Refactor EnumAnnotations and EnumFactory (Refactor EnumAnnotations and EnumFactory #1747)
• Update reported width from div/rem to match FIRRTL results (Update reported width from div/rem to match FIRRTL results #1748)
• Scala 2.13 support (Scala 2.13 #1751)
• Fix some typo and using foreach instead of map in BoringUtils (Fix some typo and using foreach instead of map in BoringUtils #1755)
• Fix incorrect comment in ScalaDoc (Fix incorrect comment in ScalaDoc #1756)
• Bump to Scala 2.12.13 (Bump to Scala 2.12.13 #1766)
• Fix stack trace trimming across Driver/ChiselStage (Fix stack trace trimming across Driver/ChiselStage #1771)
• Remove chisel3.stage.phases.DriverCompatibility (Remove chisel3.stage.phases.DriverCompatibility #1772)
• Add file line to source link from scaladoc (Add file line to source link from scaladoc #1776)
• Fix conversions between DecoupledIO and IrrevocableIO (Fix conversions between DecoupledIO and IrrevocableIO #1781)
• Aggregate: fix typo (Aggregate: fix typo #1789)

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This discussion was created from the release Chisel 3.5 Release Candidate 1.