RegEnable implementation is correct but misleading?

[mj6363]

https://github.com/chipsalliance/chisel3/blob/b24f09c758ff2d15ac9efd5a0be2a8e7b32d8443/src/main/scala/chisel3/util/Reg.scala#L36-L47

RegEnable's implementation is straight-forward and there's no wrong behavior,
but one may expect that it would check bit width and reject if it does not match.

(due to wide-spreading type inference features in many languages, I feel like it's being more expected behavior than I felt last year)

would it be better to assert bit width equality at chisel level?