Even though $ is an accepted character in Verilog's basic identifiers. Vivado does not accept it in clock names.
A constraint file with
create_clock -name {c$arg} -period 5.000 -waveform {0.000 2.500} [get_ports {c$arg}]
results in
[Vivado 12-2270] Clock names may not contain tcl special characters: '"{};$# - Skipping 'c$arg' [/filepath]

Possible fixes

• Adjust -fclash-hdlsyn Vivado to not generate $ in basic identifiers.
• Generate more basic identifiers by default (excluding tcl special characters?).
• Never generate tcl special characters in clock names.
• Change the c$ prefix.