DDR primitive documentation

[christiaanb]

Add example of a sequence of inputs and outputs for:

clash-prelude/src/CLaSH/Explicit/DDR.hs

Lines 41 to 58 in 3cc789c

	-- | DDR input primitive
	--
	-- Consumes a DDR input signal and produces a regular signal containing a pair
	-- of values.
	ddrIn
	:: ( HasCallStack
	, fast ~ 'Dom n pFast
	, slow ~ 'Dom n (2*pFast))
	=> Clock slow gated
	-- ^ clock
	-> Reset slow synchronous
	-- ^ reset
	-> (a, a, a)
	-- ^ reset values
	-> Signal fast a
	-- ^ DDR input signal
	-> Signal slow (a,a)
	-- ^ normal speed output pairs

and

clash-prelude/src/CLaSH/Explicit/DDR.hs

Lines 131 to 142 in 3cc789c

	-- | DDR output primitive
	--
	-- Produces a DDR output signal from a normal signal of pairs of input.
	ddrOut :: ( HasCallStack
	, fast ~ 'Dom n pFast
	, slow ~ 'Dom n (2*pFast))
	=> Clock slow gated -- ^ clock
	-> Reset slow synchronous -- ^ reset
	-> a -- ^ reset value
	-> Signal slow (a,a) -- ^ normal speed input pairs
	-> Signal fast a -- ^ DDR output signal
	ddrOut clk rst i0 = uncurry (withFrozenCallStack $ ddrOut# clk rst i0) . unbundle