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387 Open 1,252 Closed
387 Open 1,252 Closed
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Issues list

Inout port not working with array replication operator pending-verification This issue is pending verification and/or reproduction
#4371 opened May 3, 2024 by alchitry
1
Inout can't be read with constant value pending-verification This issue is pending verification and/or reproduction
#4370 opened May 3, 2024 by alchitry
1
Inconsistent simulation before and after yosys synthesis pending-verification This issue is pending verification and/or reproduction
#4369 opened May 3, 2024 by WeneneW
1
Spurious warnings "select out of bounds on signal" when there is no such thing ... bug
#4363 opened Apr 29, 2024 by smunaut
1
write_smt2: "-wires" option leads to inequivalent descriptions pending-verification This issue is pending verification and/or reproduction
#4361 opened Apr 27, 2024 by YikeZhou
opt: no "-purge" option but public names removed bug
#4357 opened Apr 25, 2024 by YikeZhou
2
Should -nomx8 be the default for the GateMate? pending-verification This issue is pending verification and/or reproduction
#4355 opened Apr 23, 2024 by spth
Manual title page should have yosys version number feature-request
#4354 opened Apr 23, 2024 by spth
Crash in yosys-abc pending-verification This issue is pending verification and/or reproduction
#4352 opened Apr 22, 2024 by maliberty
"ERROR: Assert `count_id(wire->name) == 0' failed in kernel/rtlil.cc:2143" when using synth_{ice40,ecp5} on simple design bug
#4349 opened Apr 20, 2024 by cr1901
synth_* passes should call check -mapped
#4348 opened Apr 20, 2024 by nakengelhardt
Another out-of-memory problem with for loop pending-verification This issue is pending verification and/or reproduction
#4345 opened Apr 19, 2024 by YikeZhou
Assertion Failure in AST Processing: node->bits == v at frontends/ast/ast.cc:855 pending-verification This issue is pending verification and/or reproduction
#4335 opened Apr 14, 2024 by 1353369570
Latch inferred for x signal bug
#4325 opened Apr 8, 2024 by spth
4
Reduce default severity of Verific messages that produce warnings on commonly used coding styles
#4324 opened Apr 8, 2024 by nakengelhardt
Parameters in other packages SystemVerilog Issues and questions related to SystemVerilog wontfix
#4318 opened Apr 4, 2024 by pentin-as
2
Assertion Failure in genrtlil.cc When Handling Signedness Issue Description: pending-verification This issue is pending verification and/or reproduction
#4307 opened Apr 1, 2024 by 1353369570
1
Yosys Fails to Detect Syntax Violations According to Verilog Standards wontfix
#4306 opened Apr 1, 2024 by 1353369570
2
ERROR: Visited AIG node more than once; this could be a combinatorial loop that has not been broken pending-verification This issue is pending verification and/or reproduction
#4291 opened Mar 21, 2024 by DmitryZlobec
2
Hang on a loop when write_cxxrtl bug cxxrtl
#4290 opened Mar 20, 2024 by 1353369570
4
Performance regression in Yosys 0.39 pending-verification This issue is pending verification and/or reproduction
#4280 opened Mar 13, 2024 by whitequark
6
opt_merge merges $assert cells discuss to be discussed at next dev jour fixe (see #devel-discuss at https://yosyshq.slack.com/)
#4278 opened Mar 12, 2024 by KrystalDelusion
@povik
1
Use of system functions in localparam value prevents resolution of port
#4275 opened Mar 11, 2024 by nakengelhardt
1
Keep attribute not working as expected pending-verification This issue is pending verification and/or reproduction
#4272 opened Mar 10, 2024 by hpretl
9
AST fails to handle implicit wires properly bug
#4263 opened Mar 6, 2024 by ylm
3
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