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ProGe: external ports of custom FUs not added to testbench #116

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RiPeloso opened this issue Mar 12, 2021 · 1 comment
Open

ProGe: external ports of custom FUs not added to testbench #116

RiPeloso opened this issue Mar 12, 2021 · 1 comment

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@RiPeloso
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HDBeditor correctly creates external ports for custom FUs that are present in tta0.vhdl but the testbench (proch_arch.vhdl) has no instantiation of those ports so they have to be added manually. To access the ports globally, also the testbench.vhdl has to be corrected accordingly.

@TopiLeppanen
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Hi,
Yep, you seem to be correct. Would be a nice feature to have the external ports to propagate also through to the testbench, and probably not too difficult to implement. Unfortunately, I don't have time to look into it closer right now, but this should eventually be corrected.

There's also the question what to do with those external ports in the end. I guess propagating to the top-most level of the testbench would be the minimal thing, and then let the RTL compilation fail if the user doesn't map any signals into them. After all, implementing the testing for external signals is left for the user to manage. Sometimes the user could want to map them outside of the testbench or alternatively instantiate their own testbench component inside the autogenerated one.

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