20201010_4c8ca86 Release

This is a development release (from the dev branch)

Raw changes since last development release are:

87c303980 Fix hang when displaying Calibration Summary in 12BPP mode
35ae5bf80 Update default profile names
11178868c Rename some profiles
eaf25be6a Fix some problems with continuous calibration
29593c08b Improvements to continuous calibration
0bdb63203 Rework continuous calibration to use absolute rather than relative updates which caused problems due to rounding errors
fe00be44d Fix calculation of vsync period with interlaced sources
8d5350a67 Update Electron profiles including mux setting on 3 bit board
e1abf0cb5 Update profiles
9ab7aa393 Improve 24Mhz mode 7 auto calibration
2e409cf6d Workaround calibration issue with very overclocked CPLD
fd410694f Update profiles
78ed4408f Fix some issues with mode 7 calibration on V9 CPLD and with x6 multiplier & update some text
878655d45 Disable clamp signal in TTL 1 bit mode
796a4e676 Support RGB CPLD V9.1
f629b1d95 update CPLD folder with RGB CPLD V9.1
66b83bb53 Update 12bit RGB CPLD to V9.1 with input multiplex signal
c12e0c6b5 Update profiles
aacb1d844 Fix half pixel bit setting with V9 cpld
19c70aefe Update simple mode menus
851d7c656 Fix 3 bit firmware folder issue
ccce4625b Fix status line in recovery menu
cac2f2fae Fix problem with 16bpp frame buffer in CPLD recovery mode
de298fe97 Rename some menu options in sampling menus
3c2adfcb1 rename some profiles
85e2d68f8 rename CPLD files
800f2d089 Enforce CPLD update after software update
36ee5a7c1 Update CPLD firmware
1dd212c53 Update profiles
50f31ff62 Update V7 release file
8812b929c Update RGB V7 VHDL to fix mux bug
b01a545cd Old V8 version of RGB CPLD with BBC support (may be deprecated)
d79c19f35 Update 12 bit RGB CPLD to V9.0 with support for 3 and 4 dividers, one bit per pixel and extra delay bit (All for high pixel clock rates) - BBC mode 7 support removed.
956af488b Add support for clock divide by 3 and 4 and 1 bit per pixel with additional delay bit (for high pixel clock rates)
36e868acf Limit CPLD clock to 200Mhz and lowest auto display frequency to 48Hz
d485484a0 Use interlaced setting in autoswitch detect
4217ba42c Update profiles
762a78fe8 Don't update DACs when switching to Vsync
4b2d26e6d Fix "all offsets" issues
f8ba68978 Save EDID at same time as log
6c3a23b99 Update labyrinth workaround for 12 Mhz divider set to 6
2d6b22ba9 Update profiles
605aa1a08 Update CPLD folder
f79b32931 V7.6 xsvf file
300fd29db Update 24Mhz CPLD to V7.6
25b701c5f Support 24 Mhz CPLD V7.6
c2de3bd1d Ensure CPLD config updated
e6ea2a9d7 Add memory log with save option
88999f60d Remove framedrop leeway
cc985030c Fix trailing edge timestamp issue
e6866231a Fix timing issue with EGA vsync detection
4e00fb5f1 Fix CPLD recovery mode key scan
045b4ded9 Add resolution & frequency message at startup
2a402abf4 Update EDID and auto 50Hz support
cde427a9c Update config.txt
572cddf1c Update default profiles
4ec0e9564 Update resolutions
f23b0b103 Read EDID info to determine 50Hz support
ef4e85024 Update profiles
5978548d4 Update pi frame rate message
746741443 Change SW1 power on resolution recovery in simple mode
d1b83db95 Update profiles
8dc066597 Fix vsync polarity change detection
9a6434d9f Fix sync polarity detection with sync on Y/G
8bae7f2c4 Tweak auto refresh setting
84d81208a Update Amiga profiles
5f5d98a53 Add auto resolution and refresh rate
c89cf1a92 Fix auto profile switching with composite sync
68f4e98ae Fix Amiga interlaced video off by 1 line
70249a3a9 Update profiles
4069e4b16 Force AC coupling with Issue 1 & 2 analog boards
b3bc2ffb3 Add separate 24Mhz profile folder support
413c451c4 Update profiles
d033782eb Fix inverted clock edge detection in simple mode

20200916_6310e8c Release

This is a development release (from the dev branch)

Raw changes since last development release are:

5bfbe2e92 Restore analog board selection except for issue 4
430d09aaf Fix screencap crash bug
592e7535f Add Amiga super denise profile
f27f475f4 Update Atari 800XL profile
636d6bbf6 Rename Overscan to Crop Border and V adjust to Swap Aspect
cf66efb0d Update profiles
47652705f Update Vertical adjust to stretch 625 and squash 525 line sources
f494ce6ee Update profiles
398ce6389 Move single button mode detection to default.txt
b2ccc2ad4 Allow overscan setting to work in integer scaling mode (actually crops)
441c9089e Fix Atari GTIA offset calculation
531f63512 Hide Issue 1 & 2 analog board support
5b6104e40 Add pixel delay option to 12 bit simple mode
d45f48566 Improve reliability of simple mode detection
08c35cf74 Update ST profile
091218066 Simplify 9 and 12 bit capture
9700c58e7 Fix capture scaling issue
ab9fe0037 Add scanline inhibit message and fix double width screencap issue
3e5aaf150 Add TEA1002 palette and Aquarius profile
33c1cf736 Fix some screencap bugs

20200908_ff298ac Release

This is a development release (from the dev branch)

Raw changes since last stable release are:

553acd3f6 Add missing NTSC source file
e77fc693f Update firmware folder
7b1236476 Add 12 bit extender board
e484ec8ad Add 12 bit pcb design
f5c4d0b78 Update profiles
4f39c8867 Limit vsync retry counter
fd20f4d26 Fix hsync timing calculation
9a5af50d9 don't retry vsync measurement if no sync
c97894b0d Add 9 bits per pixel capture modes
653756b03 Update profiles
ff7ebfb16 Handle malformed vsync pulses (Apple II)
d35562f59 Add delay after fieldsync when measuring field time
70c7fb4f0 Add vertical stretch to display 625 sources with 525 aspect ratio
4e928fcf1 Add vertical stretch option & tweak one button mode
125245e56 update profiles
ca73d7501 Add screencap option to single button mode
8ee368fdf Add Atari 800 GTIA support
5bf568a34 Add resolution files for 1680x1050
487e5e258 Support new 9bpp and 12bpp CPLD bit order in v8.5
741f7f458 Update RGB CPLD to v8.5 with reordered 6x2 and 12BPP RGB bits plus 9BPP mode.
b15fd4b1f Rename vhdl_RGB_8bit to vhdl_RGB_12bit
e997a48f9 Update 6 bit CPLD to v7.5
7611305c4 Update profiles
3174fb936 Only filter equalising pulses in interlaced vsync mode
04b0397c6 Fix high pixel rate HDMI outputs like 2560x1440
119559b29 Update profiles
98213226c Update resolutions
702aa7606 Update default genlock line from 35 to 45 in profiles
c45372e81 Update equivalence for 16BPP
ff36dda34 Update 24Mhz Mode 7 profiles
35425a224 Update cpld folder
bdc1f5dec Add 12 bit cpld references
3b59439a8 Update cpld firmware
853d95596 Update profiles
e7b3289b9 Add divider workaround for v7.5 cpld
ebaed42a6 Fix interpolated scaling issue with 720x576 mode
29682a570 Add overclocking options
66bdc59c0 Update profiles
8c0c3952a Move timestamp to leading edge
98afb6dbb Fix single edge detection bug
f594a75ab Add one button mode file
24f013790 Move timestamp detection to active edge
b35881da8 Add button reverse option for single button mode
018c21958 Add multiple sync edge options in simple mode
7578a3a50 User GPIO 16 for the button. Create gerber files.
179e91a66 Add single button menu operation option
78509d7b9 Add switch connector and slightly re-arrange xor gates
6df506f41 Improve leading edge sync timing in fast mode
dc1f5e5ec Fix RPI3 build issue
20ccba244 Update Amiga profiles
cc3ec076d Remove temporary divider test code
6c6d63f55 Update simple profiles
9d11af6b0 Update c64 profile
53a55a3b7 Fix font selection bug
a908c2dbd Update YUV CPLD to V9.0
2e8b81174 Update RGB CPLD to V8,4 with 12 BPP support
afba3f10a Set pullups / pulldowns for key switches and auto detect pins
34db533fc Only allow interlace detection when video type is interlaced or bbc mode7 detection enabled
de9b6b445 Update firmware
d30db84a5 Update profiles
c5f99e917 Fix simple board detection, sync detection and yuv offset bugs
60f1cef88 Add sync edge option for simple mode and improve profile interchangeability
ec04f8ce5 Add support for Amiga interlaced sync and equalising pulses
bc4c75bc7 remove SKIP_PSYNC_NO_H_SCROLL macro
449fb5cab Move mux from GPIO to register bit
c822ed1c7 Optimise timing of capture loops by moving stack instruction
a19f39a71 Change design name from amiga to simple to support other simple designs
d02db074c Whitespace
3743177d4 Initial support for c0pperdragon's Amiga board
3c45188ec Adapter board to attach the RPi to the Amiga's Denise chip.
a6764f134 Add 16BPP screen capture
03709bbb8 Disable scanlines in interlaced mode
78a80e06d Add scaling sanity check
33c0a79a8 Add interlaced video support and improve 12 bit capture / 16BPP frame buffer
588dd6b8b Update profiles
fa9940296 Improve 12x20 / 8x8 font selection
5ce839078 Further updates to 16BPP support
94385354d Rework osd responsiveness changes
5e907819b Add fast 12bpp capture loop
d7a22fb6a Fix some bugs with 12 BPP capture
eb439e7c5 Merge RGB and YUV sampling file formats so profiles are interchangeable between CPLDs
03bae3267 Update profiles for merged file format
b10609f90 Improve osd responsiveness by eliminating duplicate screen update
8e31c5fc7 Update profiles
15b43eec7 Add 12BPP capture & 16BPP frame buffer support
de2e4e7b0 Rework overscan setting into zoom option 0%-100% in 10% steps (interpolation only) Also rename scaling settings
fbd08f3f4 Add palette menu with brt/cont/sat/tint/gamma adjustment for all palettes
e5f484387 Update Commodore 64 palette based on colodore algorithm
2f5172858 Update profiles
839ad34a1 Update cpld firmware folder
bbedbf235 YUV_6bit renamed to YUV_8bit
3f9656f3b Add missing YUV jedec
cfe496d19 Update YUV CPLD to 8.3 - Allow separate 4 level mode on Y and UV
4b513314b Update 8 bit RGB CPLD to V8.1 - Add 8 bit capture mode
f39e17e29 Add 8 bit and 4 level RGB/YUV support
141168b98 Remove recalibration on lock fail (not required as continuous recalibration)
3d879efa7 Clip vertical comparison window
2bab60f37 Add vsync measurement retry logging
55ef77ace Update RGB CPLD to v8.0
037697227 Update profiles
d0ed13636 Fix issue with h scaling on widescreens
e814dcd4d remove interlace detection from measure_vsync() (was not used) and add retry counter for reliable measurement
6163cddda Fix ntsc status update and instruction re-ordering
828d6dfa5 Improve NTSC artifact auto switching
250a91f84 Change Mux names
91564b9e8 Add Commodore 64 support and tweak vertical sync jitter correction
6b2f6f8ef Fix scaling issue when h or v offsets went negative
7f575bf10 Add flywheel vertical sync to eliminate vertical jitter caused by thermal drift of vsyncs generated by RC monostables
fe2090f0c Fix display of final calibration value in YUV mode
729011b0c Inhibit palette dimming when adjusting NTSC values
05ad8fdc8 Improve NTSC artifact decoding
e069b7602 Fix NTSC artifact disable bug
78aa61485 Add colour burst detection to auto switch NTSC artifact on/off
d98679de8 Update profiles
409e3bbe5 Update firmware folder
35258cda7 Add auto scaling option
012487581 Change PAL switch to behave differently in 3 and 4 level modes
b1b437b0d Update DAC names and palettes
44b82f083 Add support for M62364 DAC on new analog board
465c6be3f Add 4 level RGB/YUV analog interface support
44b1116d9 Update profiles
521b7e35a Rename CPLD folders
c4e78ef06 Rename profiles folders
c49f1d8c9 Update profiles
869a81236 Starting point for 8 bit RGB.
26a7e9d83 Change L,B,A to Y,U,V respectively to clarify the signal sources
e04279bcf Update YUV CPLD: Remove UV Filter, add clamp disable, Sync source switch and 4 level YUV support
b7e3b1c5f RGB CPLD release files v7.4
168c617b1 Update RGB CPLD to inhibit clamp pulse in DC mode
419360643 Adjust unused DAC values to support MAX9142/4
8062a2acc Update profiles
948179621 Refactor scaling setting to allow for future auto option
2d73e8bf3 Hide files beginning with '.' (Mac resource forks)
3b577b796 Inhibit mode7 for CPLD recovery menu
fcbd9c32a Fix Configuration restored message
ba53fcdb8 Add CPLD erase function by deleting file (no button presses required)
c0de6494b Always dim menu background in mode 7
b45aec7d2 Update Profiles for NTSC Artifacting
c3d73fa35 Additional NTSC scanline fix
e76525c1b Fix scanlines when NTSC artifacting
894b8b632 Add NTSC Artifact colours
057965b8e Add continuous PLL and vsync timing update

20200504_d19df1c Release

Introduction

This is a stable release, the first since December 2018. It's a major update to all aspect of the system.

Hardware Improvements

• Support for new 6-bit/8-bit capture hardware
• Support for analog frontends with software controlled DACs and various t
  ermination options
• Backwards compatible with all existing hardware
• 4-bit/pixel and 8-bit/pixel framebuffers
• 3-bit and 6-bit capture modes
• Multiple pixel sampling options
• Ability to program the CPLD from the Pi (documentation is available to m
  odify existing 3-bit boards to have this capability, through the addition
  of four wires)
• Seperate CPLDs for RGB and YUV capture
• CPLD recovery mode
• Auto-clamping

New Features

• Screen Capture as PNG to SD Card (different scaling options)
• Variable scanline intensity
• Adjustable border colour
• Extensive information screens
• In-Band Palette Control (similar to VideoNuLA, experimental)

Better Image Quality

• Multiple scaling/interpolation/overscan options
• Auto-size the capture area to better suite different resolutions
• Pixel aspect ratio control
• Improved support for low resolution systems
• Genlock improvements
• Auto-detect sync polarity
• Sync-loss detection

Usablility

• Completely redesigned menu system, with variable font sizes
• Ability to save settings
• Ability to restore original settings
• Multiple Profiles

Extensibility

• User definable Profiles
• User definable Resolutions
• User definable Palettes
• User configurable button actions

Multi-System Support

• Acorn Atom
• Acorn BBC Model B / Master
• Acorn Communicator
• Acorn Electron
• Amstrad CPC
• Camputers Lynx
• Color Genie
• Commodore 128 (80 coluln TTL text output only)
• Dragon 32
• IBM PC CGA
• IBM PC EGA
• IBM PC MDA
• IBM PC VGA (9-pin TTL only, aka EGA+)
• Nascom II
• Olivetti Prodest PC1
• Oric 1
• Sinclair QL
• Sinclair Spectrum 48K (no bright colours)
• Sinclair Spectrum 128K +2
• Sinclair Spectrum 128K +2A
• Sinclair Spectrum 128K +3
• Sinclair ZX80
• Sinclair ZX81
• Superboard II
• Tandy Co Co
• UK101

20200417_5875bf0 - Release Candidate 10

Profiles: Adjust Model B profiles

Change-Id: Ia9afdbe001747c8a5b64f885633fbddcb26947c6

20200406_56d2997 - Release Candidate 9

Update profiles

20200320_8436521 - Release Candidate 8

Add Commodore 128 80 column profile

20200310_28e0f5f - Release Candidate 7

Remove 'INFO:' from logging and reduce lock status logging to 6 chars…

…+CR/LF so it will fit in the 8 char mini uart transmit FIFO

20200224_6e0d72e - Release Candidate 6

Fix BBC micro analog profile mux error

20200217_19cc272 - Release Candidate 5

Force clock tolerance to 0 in all setup modes