/
ms32.cpp
2755 lines (2225 loc) · 137 KB
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ms32.cpp
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// license:BSD-3-Clause
// copyright-holders:David Haywood,Paul Priest
/* Jaleco MegaSystem 32 (Preliminary Driver)
- hardware tests are needed to establish how the mixing really works (and interrupt source etc.)
Used by Jaleco in the Mid-90's this system, based on the V70 processor consisted
of a two board set up, the first a standard mainboard and the second a 'cartridge'
The actual Mega System 32 PCB mobo only outputs mono sound. There is a connector on
the PCB for a second speaker but it is still only in mono (no stereo effects in the music).
-- Hardware Information (from Guru) --
MS32 Motherboard
----------------
PCB ID : MB-93140A EB91022-20079-1
CPU : NEC D70632GD-20 (V70)
SOUND : Z80, YMF271, YAC513
OSC : 48.000MHz, 16.9344MHz, 40.000MHz
RAM : Cypress CY7C199-25 (x10)
Sharp LH528256-70 (x5)
Sharp LH5168D-10 (x1)
OKI M511664-80 (x8)
DIPs : 8 position (x3)
OTHER : 5.5v battery
Some PALs
2 pin connector for right speaker (sound out is STEREO)
Custom chips:
JALECO SS91022-01 (208 PIN PQFP)
JALECO SS91022-02 (100 PIN PQFP)
JALECO SS91022-03 (176 PIN PQFP) *
JALECO SS91022-05 (120 PIN PQFP) *
JALECO SS91022-07 (208 PIN PQFP)
JALECO GS91022-01 (120 PIN PQFP)
JALECO GS91022-02 (160 PIN PQFP)
JALECO GS91022-03 (100 PIN PQFP)
JALECO GS91022-04 (100 PIN PQFP) *
ROMs: None
Chips marked * also appear on a non-megasystem 32 tetris 2 plus board
MS32 Cartridge
--------------
Game Roms + Custom Chip
The Custom chip provides the encryption:
Desert War - Custom chip: JALECO SS91022-10 9513EV 367821 06441
Game Paradise - Custom chip: JALECO SS91022-10 9515EV 420201 06441
Gratia (set 2) - Custom chip: JALECO SS91022-10 9513EV 370121 06441
Tetris Plus 2 - Custom chip: JALECO SS91022-10 9513EV 370121 06441
Best Bout Boxing - Custom chip: JALECO SS92046-01 9338EV 436091 06441
H.Quiz Nettou - Custom chip: JALECO SS92046-01 9338EV 436091 06441
PK Soccer V2 - Custom chip: JALECO SS92046-01 9338EV 436091 06441
Tetris Plus - Custom chip: JALECO SS92046-01 9412EV 450891 06441
Angel Kiss - Custom chip: JALECO SS92047-01 9423EV 450891 06441
Gratia (set 1) - Custom chip: JALECO SS92047-01 9423EV 450891 06441
kirarast - Custom chip: JALECO SS92047-01 9425EV 367821 06441
P47-Aces - Custom chip: JALECO SS92048-01 9410EV 436091 06441
Custom chips are 144 pin PQFP, some times mounted on a small plug-in board silkscreened SE93139 EB91022-30056
Other examples are surface mounted directly the to ROM cart.
others are unknown
Notes
-----
Some of the roms for each game are encrypted:
16x16x8 'Scroll' Tiles (Non-Roz BG Layer)
8x8x8 'Ascii' Tiles (FG Layer)
The only difference between the two Gratia sets are the encrypted ROMs in each set (they use
different custom chips). The program ROMs are the same, as is all non encrypted graphics data.
It's been verified that when the encrypted data is decrypted with it's respective algorithms
the data in both sets match 100%
ToDo / Notes
------------
Z80 + Sound Bits
Priorities (code in tetrisp2.cpp doesn't use all of the priority ram.. and doesn't work here)
- some games require completely reversed list processing!
Dip switches/inputs in t2m32 and f1superb
some games (hayaosi2) don't seem to have service mode even if it's listed among the dips
service mode is still accessible through F1 though
Fix Anything Else (Palette etc.)
Not sure about the main "global brightness" control register, I don't think it can make the palette
completely black because of kirarast attract mode, so I'm making it cut by 50% at most.
- brightness control also breaks other games in various places, eg gametngk everything going dark
when bomb is used, p47 aces intro?
gametngk seems to need some kind of shadow sprites but the only difference in the sprite attributes is one of the
priority bits, forcing sprites of that priority to be shadows doesn't work
tetrisp needs shadows as well, see the game selection screen.
The above might be related to the second "global brightness" control register, which is 000000 in all games
except gametngk, tetrisp, tp2m32 and gratia.
horizontal position of tx and bg tilemaps is off by 1 pixel in some games
bbbxing: some sprite/roz/bg alignment issues
gratia: at the beginning of a level it shows the level name in the bottom right corner, scrolling it up
and making the score display scroll out of the screen. Is this correct or should there be a raster
effect keeping the score on screen? And why didn't they just use sprites to do that?
gratia: the 3d sky shown at the beginning of the game has a black gap near the end. It would not be visible
if I made the "global brightness" register cut to 100% instead of 50%. Mmmm...
gratia: the 3d sky seems to be the only place needed the "wrap" parameter to draw_roz to be set. All other
games work fine with it not set, and there are many places where it definitely must not be set.
gratia: at the beginning of the game, before the sky appears, the city background appears for
an instant. Missing layer enable register?
background color: pen 0 is correct for gametngk, but wrong for f1superb. Maybe it depends on the layer
priority order?
roz layer wrapping: currently it's always ON, breaking places where it gets very small so it gets
repeated on the screen (p47aces, kirarast, bbbxing, gametngk need it OFF).
gratia and desertwr need it ON.
there are sprite lag issues - sprites should be framebuffered
missing clipping window effect in gametngk intro
Not Working Games
-----------------
f1superb - the road is always rendered as straight.
- the game has a road layer and extra roms for it
- there is an unknown maths DSP for protection
Jaleco Megasystem 32 Game List - thanks to Yasuhiro
---------------------------------------------------
P-47 Aces (p47aces)
Game Tengoku / Game Paradise (gametngk)
Tetris Plus (tetrisp)
Tetris Plus 2 (tp2m32)
Best Bout Boxing (bbbxing)
Wangan Sensou / Desert War (desertwr)
Second Earth Gratia (92047-01 version) (gratia)
Second Earth Gratia (91022-10 version) (gratiaa)
F-1 Super Battle (f1superb)
Idol Janshi Su-Chi-Pi 2 (suchie2)
Ryuusei Janshi Kirara Star (kirarast)
Mahjong Angel Kiss
Vs. Janshi Brand New Stars
Hayaoshi Quiz Nettou Namahousou ( hayaosi3 )
Hayaoshi Quiz Grand Champion Taikai (hayaosi2)
Not Dumped:
Super Strong Warriors
Shutokou Red Zone / Super Circuit Red Zone
NOTE: Several games use the ROM cart board number for the EPROM numbers. Though several
use MB93166 for the MB-94166 cart
************************************************************************************
Notes from Charles MacDonald
----------------------------------------------------------------------------
Z80 communication
----------------------------------------------------------------------------
The system has two 8-bit registers which store bytes going from the Z80
to the V70 and vice-versa.
V70 side
$FC800000 : Writes load the Z80 sound latch and trigger a NMI.
Reads return D31-D16 = open bus, D15-D0 = $FFFF.
$FD000000 : Reads return D31-D16 = open bus, D15-D8 = $FF, and
D7-D0 = V70 sound latch, inverted.
Writes halt the system.
Z80 side
$3F10 : Reads return the contents of the Z80 sound latch, inverted.
Writes load the V70 sound latch.
To handle the inversion of sound latch data, both CPUs should invert the
data read from their respective read addresses.
*** Does NMI stay low such that further NMIs can't occur until it's ACK'd?
Well, reading 3F10-3F1F allows further NMIs which are otherwise masked.
Is /NMI line really physically held low during this time?
Or is there just a flip-flop that remains set until read, which
gates NMI?
*** Does $3F10 cause interrupt on V60 side when accessed? Or $3F20?
Could 3F20 be a V70-side interrupt request clear register?
----------------------------------------------------------------------------
Sound reset register
----------------------------------------------------------------------------
Writing a '1' to bit 0 of $FCE00038 temporarily pulses the Z80 /RESET pin
low for approximately one second, at which point it goes high again and the
Z80 resumes operation.
Setting this bit does *not* keep the Z80 reset for the duration that
it is set. It's function is that of a trigger for an automatically timed
reset pulse.
*** Measure /RESET pulse width in units of Z80 clocks.
----------------------------------------------------------------------------
V70 memory map
----------------------------------------------------------------------------
Overview
The hardware maps memory and other devices to a 64MB chunk that is
repeatedly mirrored throughout the last 1GB of the address space.
The system is set up so the V70 is halted when it accesses an unused
memory address or accesses it in an unintended way (reading write-only
locations, writing to read-only locations). Shortly thereafter the
watchdog resets the system due to inactivity.
The V70 data bus is 32-bit but is connected to a mix of 8, 16, and 32-bit
hardware. The undriven data bus bits tend to float high, though my
board had a lot of extra pull-up resistors someone added in one of
the expansion sockets. I'll try to give approximate garbage values read
from these locations when possible.
V70 memory map
C0000000-FBFFFFFF : Mirror of FC000000-FFFFFFFF
Range Acc Repeat Size Width Description
FC000000-FC1FFFFF : R/W : 32K : 8K : 8 : NVRAM
FC600000-FC7FFFFF : R/W : --- : --- : -- : Unused (return $FFFFFFFF)
FC800000-FC9FFFFF : R/W : 4b : : 16 : Z80 sound latch (out)
FCC00000-FCDFFFFF : R/W : 32b : : 32 : I/O area
FCE00000-FCFFFFFF : W/O : 8K : 4K : 16 : Video registers
FD000000-FD03FFFF : R/O : 4b : : 16 : Z80 sound latch (in)
FD180000-FD1BFFFF : R/W : 32K : 8K : 8 : Priority RAM
FD400000-FD5FFFFF : R/W : 256K : 128K : 16 : Color RAM
FE000000-FE1FFFFF : R/W : 128K : 64K : 16 : Rotate RAM
FE200000-FE3FFFFF : R/W : 8K : 4K : 16 : Line RAM
FE800000-FE9FFFFF : R/W : 256K : 128K : 16 : Object RAM
FEC00000-FEDFFFFF : R/W : 64K : 32K : 16 : ASCII RAM / Scroll RAM
FEE00000-FEEFFFFF : R/W : 128K : 128K : 32 : Work RAM
FF000000-FFFFFFFF : R/O : 2MB : 2MB : 32 : Program ROM
For example, the object RAM is 128Kx16, mapped to D15-D0 of each word.
This corresponds to a 256K space (128K x 32-bits, 16 of which are used)
that repeats every 256K within FE800000-FE9FFFFF.
1.) Data written to the LSB is stored inverted in $3F10 and triggers NMI.
Writing to D15-D8 does nothing and value read is $FF.
Writing to D31-D16 resets the machine, values read are open bus (opcodes).
All items listed are repeatedly mirrored throughout the memory ranges
they are assigned to.
This is the memory map for a Desert War boardset. Other games can add
additional hardware on the ROM board which take up memory ranges not listed
here. Consider it to be the memory map for a stock Mega System 32 mainboard.
----------------------------------------------------------------------------
I/O ports
----------------------------------------------------------------------------
The I/O area consists of 16 word locations that are mirrored repeatedly
throughout the range they are mapped to:
FCC00000 : ?
FCC00004 : Player 1, 2 and control panel inputs
FCC00008 : ?
FCC0000C : ?
FCC00010 : DIP switch inputs
FCC00014 : ?
FCC00018 : ?
FCC0001C : ?
Input details
FCC00004 : ---- ---- ---- ---- ---- ---- 4321 rldu : 1P buttons, joystick
: ---- ---- ---- ---- 4321 rldu ---- ---- : 2P buttons, joystick
: ---- ---- ---- --21 ---- ---- ---- ---- : 2P coin, 1P coin
: ---- ---- ---- ts-- ---- ---- ---- ---- : Test, service
: ---- ---- --21 ---- ---- ---- ---- ---- : 2P start, 1P start
* All inputs are active-high (1= switch released, 0= switch pressed)
* When the TILT input is asserted, the system is reset. This continues
until TILT is released. The state of TILT cannot be read.
FCC00010 : ---- ---- ---- ---- ---- ---- 1234 5678 : DIP SW2 #1-8
: ---- ---- ---- ---- 1234 5678 ---- ---- : DIP SW1 #1-8
: ---- ---- 1234 5678 ---- ---- ---- ---- : DIP SW3 #1-8
* All inputs are active-low (1= switch OFF, 0= switch ON)
----------------------------------------------------------------------------
System and video registers
----------------------------------------------------------------------------
This area is 8K long and repeats every 8K. All registers are write-only
and are mapped to D15-D0 of each word.
$FCE00000 : Screen mode control
D0 : Dot clock control (1= 24 KHz?, 0= 15 KHz)
$FCE00004 : Horizontal timing
$FCE00008 : Horizontal timing
$FCE0000C : Horizontal timing
$FCE00010 : Horizontal viewport start
$FCE00014 : Frame height
$FCE00018 : Display height
$FCE0001C : Horizontal positioning
$FCE00020 : Fine positioning adjust
$FCE00045 : IRQ acknowledge
$FCE00038 : Sound CPU reset
$FCE00050 : Watchdog reset
$FCE006xx : ROZ
$FCE00A00 : Text layer horizontal scroll #1
$FCE00A04 : Text layer vertical scroll #1
$FCE00A08 : Text layer horizontal scroll #2
$FCE00A0C : Text layer vertical scroll #2
$FCE00A2x : BG layer
$FCE00A7C : Layer related
$FCE00Exx : Coin meter + lockout
----------------------------------------------------------------------------
NVRAM
----------------------------------------------------------------------------
NVRAM is 8K, occupying D7-D0 of each word. It is mirrored every 8K-words
(32K bytes) in memory.
Remaining data bits return $FFFFF4xx.
The NVRAM consists of a low-power 8K SRAM connected to a .1F capacitor for
short-term data retention and a CR2032 lithium battery for long-term
retention. It also has a write inhibit circuit to protect RAM from spurious
writes when the voltage drops low enough to trigger a system reset.
During normal operation the write protection is transparent to the
programmer and the SRAM can be accessed normally.
----------------------------------------------------------------------------
Priority RAM
----------------------------------------------------------------------------
Priority RAM is 8K, occupying D7-D0 of each word. It is mirrored
every 8K-words (32K bytes) in memory.
Remaining data bits return $00FFFFxx.
Note that the priority RAM chip is actually 32K. The upper address lines
are tied low or high, so perhaps priority RAM is banked.
----------------------------------------------------------------------------
Color RAM
----------------------------------------------------------------------------
Color RAM is implemented with three 32Kx8 SRAMs. Every eight-byte area
within color RAM addresses one location in color RAM. The red and green
color RAMs are connected in parallel to D15-D0 respectively for even words,
and the blue color RAM is connected to D7-D0 for odd words:
MSB LSB
+$00 : ---- ---- ---- ---- rrrr rrrr gggg gggg : Red, green components
+$04 : ---- ---- ---- ---- ---- ---- bbbb bbbb : Blue component
- = Bit isn't used. Usually returns '1'.
The color RAM area is 256K in size (32K entries x 8 bytes per entry) and
is mirrored every 256K bytes in memory.
----------------------------------------------------------------------------
Rotate RAM
----------------------------------------------------------------------------
Rotate RAM is 64K, occupying D15-D0 of each word. It is mirrored every
64K-words (128K bytes) in memory.
Remaining data bits return $00FFxxxx or $0000xxxx randomly.
----------------------------------------------------------------------------
Object RAM
----------------------------------------------------------------------------
Object RAM is 128K, occupying D15-D0 of each word. It is mirrored every
128K-words (256K bytes) in memory.
Remaining data bits return $FFFFxxxx.
----------------------------------------------------------------------------
ASCII / Scroll RAM
----------------------------------------------------------------------------
ASCII / Scroll RAM is 32K, occupying D15-D0 of each word. It is mirrored
every 64K-words (128K bytes) in memory.
Remaining data bits return $0000xxxx.
----------------------------------------------------------------------------
Work RAM
----------------------------------------------------------------------------
Work RAM is 128K, occupying D31-D0 of each word. It is mirrored every 128K
bytes in memory.
----------------------------------------------------------------------------
Program ROM
----------------------------------------------------------------------------
Program ROM is 512K, occupying D31-D0 of each word. It is mirrored every
512K bytes in memory.
----------------------------------------------------------------------------
CPU information
----------------------------------------------------------------------------
Main CPU: NEC uPD70632GD-20 (200-pin PQFP, 20 MHz)
* The value of PIR for this particular chip is $00007007.
* The instruction MOV.D with a register operand uses the register
pair "rn:rn+1" as the source data. R31 is a special case; the second
register of the pair is still R31 rather than wrapping to R0.
mov.d r2, [r0] ; Write pair R2:R3 to [R0]
mov.d r3, [r0] ; Write pair R3:R4 to [R0]
mov.d r31, [r0] ; Write pair R31:R31 to [R0]
Using the immediate or quick immediate addressing mode for the source
operand causes an Addressing Mode exception, just like the uPD70616.
Sound CPU: Zilog Z80840008PSC (40-pin DIP, 8 MHz)
* NMOS type. Undocumented instruction "out (c), 0" functions normally.
*/
/********** BITS & PIECES **********/
#include "emu.h"
#include "ms32.h"
#include "jalcrpt.h"
#include "cpu/z80/z80.h"
#include "cpu/v60/v60.h"
#include "speaker.h"
#include "f1superb.lh"
/********** READ INPUTS **********/
CUSTOM_INPUT_MEMBER(ms32_state::mahjong_ctrl_r)
{
u32 mj_input;
switch (m_mahjong_input_select[0])
{
case 0x01:
mj_input = ioport("MJ0")->read();
break;
case 0x02:
mj_input = ioport("MJ1")->read();
break;
case 0x04:
mj_input = ioport("MJ2")->read();
break;
case 0x08:
mj_input = ioport("MJ3")->read();
break;
case 0x10:
mj_input = ioport("MJ4")->read();
break;
default:
mj_input = 0;
}
return mj_input & 0xff;
}
void ms32_base_state::sound_command_w(u32 data)
{
m_soundlatch->write(data & 0xff);
// give the Z80 time to respond
m_maincpu->spin_until_time(attotime::from_usec(40));
}
u32 ms32_base_state::sound_result_r()
{
// tp2m32 never pings the sound ack, so irq ack is most likely done here
irq_raise(1, false);
return m_to_main^0xff;
}
u8 ms32_state::ms32_nvram_r8(offs_t offset)
{
return m_nvram_8[offset];
}
void ms32_state::ms32_nvram_w8(offs_t offset, u8 data)
{
m_nvram_8[offset] = data;
}
u8 ms32_state::ms32_priram_r8(offs_t offset)
{
return m_priram[offset];
}
void ms32_state::ms32_priram_w8(offs_t offset, u8 data)
{
m_priram[offset] = data;
}
u16 ms32_state::ms32_palram_r16(offs_t offset)
{
return m_palram[offset];
}
void ms32_state::ms32_palram_w16(offs_t offset, u16 data, u16 mem_mask)
{
COMBINE_DATA(&m_palram[offset]);
}
u16 ms32_state::ms32_rozram_r16(offs_t offset)
{
return m_rozram[offset];
}
void ms32_state::ms32_rozram_w16(offs_t offset, u16 data, u16 mem_mask)
{
COMBINE_DATA(&m_rozram[offset]);
m_roz_tilemap->mark_tile_dirty(offset/2);
}
u16 ms32_state::ms32_lineram_r16(offs_t offset)
{
return m_lineram[offset];
}
void ms32_state::ms32_lineram_w16(offs_t offset, u16 data, u16 mem_mask)
{
COMBINE_DATA(&m_lineram[offset]);
}
u16 ms32_state::ms32_sprram_r16(offs_t offset)
{
return m_sprram[offset];
}
void ms32_state::ms32_sprram_w16(offs_t offset, u16 data, u16 mem_mask)
{
COMBINE_DATA(&m_sprram[offset]);
}
u16 ms32_state::ms32_txram_r16(offs_t offset)
{
return m_txram[offset];
}
void ms32_state::ms32_txram_w16(offs_t offset, u16 data, u16 mem_mask)
{
COMBINE_DATA(&m_txram[offset]);
m_tx_tilemap->mark_tile_dirty(offset/2);
}
u16 ms32_state::ms32_bgram_r16(offs_t offset)
{
return m_bgram[offset];
}
void ms32_state::ms32_bgram_w16(offs_t offset, u16 data, u16 mem_mask)
{
COMBINE_DATA(&m_bgram[offset]);
m_bg_tilemap->mark_tile_dirty(offset/2);
m_bg_tilemap_alt->mark_tile_dirty(offset/2);
}
void ms32_state::bgmode_w(u32 data)
{
m_tilemaplayoutcontrol = data;
if ((data) && (data != 1))
popmessage("fce00a7c = %02x",data);
}
void ms32_state::coin_counter_w(u32 data)
{
// desertwr/p47aces sets 4 here
// f1superb sets 2
machine().bookkeeping().coin_counter_w(0, data & 0x10);
machine().bookkeeping().coin_counter_w(1, data & 0x20);
}
void ms32_state::ms32_map(address_map &map)
{
/* RAM areas verified by testing on real hw - usually accessed at the 0xfc000000 + mirror */
// 0xfc000000 NVRAM (8-bits wide, 0x2000 in size)
map(0xc0000000, 0xc0007fff).rw(FUNC(ms32_state::ms32_nvram_r8), FUNC(ms32_state::ms32_nvram_w8)).umask32(0x000000ff).mirror(0x3c1f8000);
// map(0xc0008000, 0xc01fffff) // mirrors of nvramram, handled above
// 0xfd180000 Priority RAM (8-bits wide, 0x2000 in size)
map(0xc1180000, 0xc1187fff).rw(FUNC(ms32_state::ms32_priram_r8), FUNC(ms32_state::ms32_priram_w8)).umask32(0x000000ff).mirror(0x3c038000);
// map(0xc1188000, 0xc11bffff) // mirrors of priram, handled above
// 0xfd200000 palette related, unknown
// 0xfd400000 paletteram (16-bits wide, 0x20000 in size)
// 0xfd400000 object palette
// 0xfd408000 Background palette
// 0xfd410000 ROZ1 palette
// 0xfd420000 ROZ0 palette?
// 0xfd430000 ASCII palette
map(0xc1400000, 0xc143ffff).rw(FUNC(ms32_state::ms32_palram_r16), FUNC(ms32_state::ms32_palram_w16)).umask32(0x0000ffff).mirror(0x3c1c0000);
// map(0xc1440000, 0xc145ffff) // mirrors of palram, handled above
// 0xfe000000 ROZ1 VRAM (16-bits wide, 0x10000 in size)
map(0xc2000000, 0xc201ffff).rw(FUNC(ms32_state::ms32_rozram_r16), FUNC(ms32_state::ms32_rozram_w16)).umask32(0x0000ffff).mirror(0x3c1e0000);
// map(0xc2020000, 0xc21fffff) // mirrors of rozram, handled above
// 0xfe200000 ROZ1 line RAM (16-bits wide, 0x1000 in size)
map(0xc2200000, 0xc2201fff).rw(FUNC(ms32_state::ms32_lineram_r16), FUNC(ms32_state::ms32_lineram_w16)).umask32(0x0000ffff).mirror(0x3c1fe000);
// map(0xc2202000, 0xc23fffff) // mirrors of lineram, handled above
// 0xfe400000 ROZ0 VRAM?
// 0xfe600000 ROZ0 line RAM?
// 0xfe800000 object layer VRAM (16-bits wide, 0x10000 in size)
map(0xc2800000, 0xc281ffff).rw(FUNC(ms32_state::ms32_sprram_r16), FUNC(ms32_state::ms32_sprram_w16)).umask32(0x0000ffff).mirror(0x3c1e0000);
// map(0xc2820000, 0xc29fffff) // mirrors of sprram, handled above
// 0xfec00000 ASCII layer VRAM (16-bits wide, 0x4000 in size)
map(0xc2c00000, 0xc2c07fff).rw(FUNC(ms32_state::ms32_txram_r16), FUNC(ms32_state::ms32_txram_w16)).umask32(0x0000ffff).mirror(0x3c1f0000);
// 0xfec08000 Background layer VRAM (16-bits wide, 0x4000 in size)
map(0xc2c08000, 0xc2c0ffff).rw(FUNC(ms32_state::ms32_bgram_r16), FUNC(ms32_state::ms32_bgram_w16)).umask32(0x0000ffff).mirror(0x3c1f0000);
// map(0xc2c10000, 0xc2dfffff) // mirrors of txram / bg, handled above
// 0xfee00000 Scratch RAM (32-bit wide, 0x20000 in size)
map(0xc2e00000, 0xc2e1ffff).ram().mirror(0x3c0e0000);
// 0xffc00000 ROM (32-bit wide, 0x200000 in size)
map(0xc3e00000, 0xc3ffffff).rom().region("maincpu", 0).mirror(0x3c000000);
// I/O section
// TODO: mirrors like above?
map(0xfc800000, 0xfc800003).nopr().w(FUNC(ms32_state::sound_command_w)); // open bus on read?
// map(0xfcc00000, 0xfcc0001f) // input
map(0xfcc00004, 0xfcc00007).portr("INPUTS");
map(0xfcc00010, 0xfcc00013).portr("DSW");
// System Registers
map(0xfce00000, 0xfce0005f).m(m_sysctrl, FUNC(jaleco_ms32_sysctrl_device::amap)).umask32(0x0000ffff);
map(0xfce00200, 0xfce0027f).ram().share("sprite_ctrl");
map(0xfce00280, 0xfce0028f).w(FUNC(ms32_state::ms32_brightness_w)); // global brightness control
// map(0xfce00400, 0xfce0045f) // ROZ0 control registers
/**/map(0xfce00600, 0xfce0065f).ram().share("roz_ctrl"); // ROZ1 control registers
/**/map(0xfce00a00, 0xfce00a17).ram().share("tx_scroll"); // ASCII layer scroll
/**/map(0xfce00a20, 0xfce00a37).ram().share("bg_scroll"); // Background layer scroll
map(0xfce00a7c, 0xfce00a7f).w(FUNC(ms32_state::bgmode_w));
// map(0xfce00c00, 0xfce00c1f) // ???
map(0xfce00e00, 0xfce00e03).w(FUNC(ms32_state::coin_counter_w)); // coin counters + something else
map(0xfd000000, 0xfd000003).r(FUNC(ms32_state::sound_result_r));
// Extended I/O
// map(0xfd040000, 0xfd040003)
// map(0xfd080000, 0xfd080003)
// map(0xfd0c0000, 0xfd0c0003)
map(0xfd1c0000, 0xfd1c0003).writeonly().share("mahjong_select");
}
/* F1 Super Battle has an extra linemap for the road, and am unknown maths chip (mcu?) handling perspective calculations for the road / corners etc. */
/* it should use its own memory map */
void ms32_f1superbattle_state::road_vram_w16(offs_t offset, u16 data, u16 mem_mask)
{
COMBINE_DATA(&m_road_vram[offset]);
m_extra_tilemap->mark_tile_dirty(offset/2);
}
u16 ms32_f1superbattle_state::road_vram_r16(offs_t offset)
{
return m_road_vram[offset];
}
void ms32_f1superbattle_state::ms32_irq2_guess_w(u32 data)
{
irq_raise(2, true);
}
void ms32_f1superbattle_state::ms32_irq5_guess_w(u32 data)
{
irq_raise(5, true);
}
u32 ms32_f1superbattle_state::analog_r()
{
int a,b,c,d;
a = ioport("AN2")->read(); // unused?
b = ioport("AN2")->read(); // unused?
c = ioport("AN1")->read();
d = (ioport("AN0")->read() - 0xb0) & 0xff;
return a << 24 | b << 16 | c << 8 | d << 0;
}
void ms32_f1superbattle_state::f1superb_map(address_map &map)
{
ms32_map(map);
// comms RAM, 8-bit resolution?
// unsurprisingly it seems to use similar mechanics to other Jaleco games
// Throws "FLAM ERROR" in test mode if irq 11 is enabled
// irq 11 is cleared to port $1e (irq_ack_w) in sysctrl.
map(0xfd0c0000, 0xfd0c0fff).ram();
map(0xfd0d0000, 0xfd0d0003).portr("DSW2"); // MB-93159
map(0xfd0e0000, 0xfd0e0003).r(FUNC(ms32_f1superbattle_state::analog_r)).nopw(); // writes 7-led seg at very least
map(0xfce00800, 0xfce0085f).ram(); // ROZ0 control register (mirrored from 0x400?)
/* these two are almost certainly wrong, they just let you see what
happens if you generate the FPU ints without breaking other games */
// map(0xfce00e00, 0xfce00e03).w(FUNC(ms32_f1superbattle_state::ms32_irq5_guess_w));
// bit 1: steering shock
// bit 0: seat motor
// map(0xfd0f0000, 0xfd0f0003).w(FUNC(ms32_f1superbattle_state::ms32_irq2_guess_w));
// Note: it is unknown how COPRO irqs actually acks,
// most likely candidate is a 0x06 ping at both $fd1024c8 / $fd1424c8
// irq_2: 0xffe00878 (really unused)
// irq_5: 0xffe008ac
// irq_7: 0xffe008ea (basically identical to irq_5)
// COPRO 1
map(0xfd100000, 0xfd103fff).ram(); // used when you start enabling fpu ints
map(0xfd104000, 0xfd105fff).ram(); // uploads data here
// COPRO 2
map(0xfd140000, 0xfd143fff).ram(); // used when you start enabling fpu ints
map(0xfd144000, 0xfd145fff).ram(); // same data here
// map(0xfd440000, 0xfd47ffff).ram(); // color?
map(0xfdc00000, 0xfdc1ffff).rw(FUNC(ms32_f1superbattle_state::road_vram_r16), FUNC(ms32_f1superbattle_state::road_vram_w16)).umask32(0x0000ffff);
map(0xfde00000, 0xfde1ffff).ram(); // scroll info for lineram?
// map(0xfe202000, 0xfe2fffff).ram(); // vram?
}
/* F1 Super Battle speculation from nuapete
Hi David,
I had a first look at f1superb, this is what I found so far.
The sprite RAM is updated in a few places, but taking one of the
sprite RAM updating routines at 0xFFE47B6F which is used to draw stuff
that should move around, I see that the information is copied from
buffers with these bases:
FEE11000 = x position data
FEE11100 = y position data
FEE11200 = priority etc data
You already spotted that loop at FFE19D1C that fills the "y position"
buffer from an array of static values. The buffers are refilled again
by the routine at 0xFFE17581. You can see that the data is sourced
from another buffer at 0xFD100000 (currently not mapped in the driver,
but I mapped it in for testing...)
If you backtrace that call, it comes from irq 5 and 7. (They have
identical ISR code) so I tried adding in a trigger for irq 7. Now the
values are populated, and stuff moves, but everything moves way too
much, it's all over the place, eventually the car zooms off up into
the sky. It gets clearer as you map less and less of the RAM at
0xFD100000. With just 1K or so mapped, you can see the buildings in
the background veer about in quite a promising manner. (The patch you
put in loses effect with irq 5 or 7 hooked up, because they repopulate
the Y coords too.)
I took a closer look at the interrupts. Handily enough they left some
strings in the ROM with names for each interrupt :) They aren't quite
in the order of the interrupts, but I matched the unreferenced strings
up to the valid interrupts as well as I could and then tried to
confirm them by looking at the code. The ROM string is in quotes.
FFE00DE8 ; irq_0 probably "1msec interrupt"
FFE00DF4 ; irq_1 "sound cpu interrupt"
FFE00878 ; irq_2 probably "fpu 1-1 interrupt"
FFE00884 ; irq_3 unused and labeled "fpu 0-1 interrupt"
FFE00898 ; irq_4 unused and labeled "fpu 1-0 interrupt"
FFE008AC ; irq_5 probably "fpu 0-0 interrupt", x coords (and y) populated from here
FFE008D0 ; irq_6 unused and labeled "option 2 interrupt"
FFE008E4 ; irq_7 same as 5 - probably "option 1 interrupt"
FFE01034 ; irq_9 VBL at 60Hz this would be "16msec interrupt"
FFE01094 ; irq_10 loads of processing in the 0xfc000000 area : must be "32msec interrupt"
FFE00E14 ; irq_11 "communication interrupt"
irq_0 is sort of confirmed by the "hayaosi2 needs at least 12 IRQ
0..." comment. irq_1 I see is already known. irq_9 is known, irq_10 I
tried halving the frequency it runs at, no effect. irq_11 can be
pretty much confirmed as comms by the code there and the use of
MOVT/MOVZ to i/o with 16 bit device based at FEE00000, so that leaves
the ones that do the sprite info loading, this is where it starts to
look less promising :(
Between irqs 2,3,4,5,7 the only unused strings in the ROM are the four "fpu
* interrupt" and the "option 1".
Irqs 2,5,7 all do "or.w #6, FD1424C8[PC]" ,so they are all probably
"fpu * interrupt".
I'm thinking that the stuff is dumped in that RAM at 0xFD100000 that's
not used by other games and then some FPU operation is carried out on it
before it's grabbed by the sprite copy code. The "option" stuff, may be
they tried a few different ways to work out the sprite coords? There's
one more intersting string at 0xFFE481FC referenced from unused code
at 0xFFE47FBC. It looks like debugging dump of sprite coordinate and
angle information.
I had a scout around for photos or anything of the PCB to see if there
is some sort of DSP or FPU on it, but I can't find anything useful. I
suspect it's not a generic MegaSystem 32 PCB, going by the extra
stuff, and also the IRQ 5/7 breaks the other games. I see a vanilla
one for sale, but I'd guess there's no point me picking it up for a
closer look because it won't have whatever the extras are.
I'll keep looking a bit more, but I think that 0xFD100000 buffer is
processed by something external that triggers irq 5 or 7 when it's
done. I might see something obvious by looking at the values in
fact... I'd be interested to know what you think, or if there's any
chance of finding out if there's stuff like dual port RAM or something
that might qualify as a FPU?
Hi David,
On the f1superb stuff, I've traced the sprite elements right back to
the arrays for each race track in ROM that they are sourced from. The
only processing they get is in that "fpu" interrupt. I've figured out
the structure of the "fpu" device, it uses two arrays of static info
loaded from the ROM at boot, two identical sets of registers, and 4
banks of volatile data read in every frame or so from the ROM race
track arrays (although it looks like one was not used in the end).
There's a sequence of four operations ivolving the "fpu" carried out
to prepare the info which then gets copied back to RAM and then to
sprite RAM. I'll capture the relevant info and see if I can figure out
what the operations might be, my maths isn't up to much though...
*/
/*************************************
*
* Generic port definitions
*
*************************************/
static INPUT_PORTS_START( ms32 )
PORT_START("INPUTS")
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
PORT_BIT( 0x00000100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
PORT_BIT( 0x00000200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
PORT_BIT( 0x00000400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
PORT_BIT( 0x00000800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
PORT_BIT( 0x00001000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
PORT_BIT( 0x00002000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
PORT_BIT( 0x00004000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
PORT_BIT( 0x00008000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_SERVICE1 )
// mapping to F1 key because there may be a specific service dip as well
PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
PORT_BIT( 0x00100000, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x00200000, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(1)
PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(2)
PORT_BIT( 0x01000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x02000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x04000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x08000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x10000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x20000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("DSW")
PORT_DIPUNUSED_DIPLOC( 0x00000001, 0x00000001, "SW2:8" )
PORT_DIPUNUSED_DIPLOC( 0x00000002, 0x00000002, "SW2:7" )
PORT_DIPUNUSED_DIPLOC( 0x00000004, 0x00000004, "SW2:6" )
PORT_DIPUNUSED_DIPLOC( 0x00000008, 0x00000008, "SW2:5" )
PORT_DIPUNUSED_DIPLOC( 0x00000010, 0x00000010, "SW2:4" )
PORT_DIPUNUSED_DIPLOC( 0x00000020, 0x00000020, "SW2:3" )
PORT_DIPUNUSED_DIPLOC( 0x00000040, 0x00000040, "SW2:2" )
PORT_DIPUNUSED_DIPLOC( 0x00000080, 0x00000080, "SW2:1" )
PORT_SERVICE_DIPLOC( 0x00000100, IP_ACTIVE_LOW, "SW1:8" )
PORT_DIPNAME( 0x00000200, 0x00000200, DEF_STR( Free_Play ) ) PORT_DIPLOCATION("SW1:7")
PORT_DIPSETTING( 0x00000200, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
PORT_DIPNAME( 0x00001c00, 0x00001c00, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:6,5,4")
PORT_DIPSETTING( 0x00000000, DEF_STR( 5C_1C ) )
PORT_DIPSETTING( 0x00001000, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x00000800, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x00001800, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x00001c00, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x00000c00, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x00001400, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0x00000400, DEF_STR( 1C_4C ) )
PORT_DIPNAME( 0x0000e000, 0x0000e000, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:3,2,1")
PORT_DIPSETTING( 0x00000000, DEF_STR( 5C_1C ) )
PORT_DIPSETTING( 0x00008000, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x00004000, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x0000c000, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x0000e000, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x00006000, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x0000a000, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0x00002000, DEF_STR( 1C_4C ) )
PORT_DIPUNUSED_DIPLOC( 0x00010000, 0x00010000, "SW3:8" )
PORT_DIPUNUSED_DIPLOC( 0x00020000, 0x00020000, "SW3:7" )
PORT_DIPUNUSED_DIPLOC( 0x00040000, 0x00040000, "SW3:6" )
PORT_DIPUNUSED_DIPLOC( 0x00080000, 0x00080000, "SW3:5" )
PORT_DIPUNUSED_DIPLOC( 0x00100000, 0x00100000, "SW3:4" )
PORT_DIPUNUSED_DIPLOC( 0x00200000, 0x00200000, "SW3:3" )
PORT_DIPUNUSED_DIPLOC( 0x00400000, 0x00400000, "SW3:2" )
PORT_DIPUNUSED_DIPLOC( 0x00800000, 0x00800000, "SW3:1" )
PORT_BIT( 0xff000000, IP_ACTIVE_LOW, IPT_UNUSED ) // Unused?
INPUT_PORTS_END
static INPUT_PORTS_START( ms32_mahjong )
PORT_INCLUDE( ms32 )
PORT_MODIFY("INPUTS")
PORT_BIT( 0x000000ff, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_CUSTOM_MEMBER(ms32_state, mahjong_ctrl_r) // here we read mahjong keys
PORT_BIT( 0x0000ff00, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME(DEF_STR( Test )) PORT_CODE(KEYCODE_F1)
PORT_BIT( 0x00100000, IP_ACTIVE_LOW, IPT_UNUSED ) /* Start 1 is already mapped in mahjong inputs */
PORT_BIT( 0x00200000, IP_ACTIVE_LOW, IPT_UNUSED ) /* ms32.cpp mahjongs don't have P2 inputs -> no Start 2*/
PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("MJ0")
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_MAHJONG_A )
PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_MAHJONG_E )
PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_MAHJONG_M )
PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_MAHJONG_I )
PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("MJ1")
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_MAHJONG_B )
PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_MAHJONG_F )
PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_MAHJONG_N )
PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_MAHJONG_J )
PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("MJ2")
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_UNKNOWN )