/
pc9801.cpp
3070 lines (2614 loc) · 124 KB
/
pc9801.cpp
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// license:BSD-3-Clause
// copyright-holders:Angelo Salese,Carl
/**************************************************************************************************
PC-9801 (c) 1981 NEC
TODO:
- proper 8251 uart hook-up on keyboard;
- text scrolling, μPD52611 (cfr. clipping in edge & arcus2, madoum* too?);
- Abnormal 90 Hz refresh rate adjust for normal display mode (15KHz).
Should really be 61.xx instead, understand how CRTC really switches clock;
- AGDC emulation, μPD72120;
- GP-IB emulation, μPD7210;
- DAC1BIT has a bit of clicking with start/end of samples, is it fixable or just a btanb?
- Write a PC80S31K device for 2d type floppies
(also used on PC-6601SR, PC-8801 and PC-88VA, it's the FDC + Z80 sub-system);
- FDC (note: epdiag FDC test looks a good candidate for all this):
- Has on board dip-switches, we currently just return 2HD/2DD autodetect;
- 3'5 floppy disks don't load at all ($4be I/O port is the extra accessor);
- fix FDC duplication: according to docs I/O ports $90-$95 are basically mirrors
with a subset of the drive related flags.
Sounds like a afterthought of having 2HD/2DD separate boards from vanilla class;
- Move vanilla FDC 2HD/2DD to a separate (legacy?) bus, and split pc9801f (default: 2DD)
from pc9801m (2HD) and vanilla pc9801 (none);
- floppy sounds never silences when drive is idle (disabled for the time being);
- epdiag throws ID invalid when run with PORT EXC on (DIP-SW 3-1 -> 0);
- CMT support (-03/-13/-36 i/f or cbus only, supported by i86/V30 fully compatible machines
only);
- SASI/SCSI support (fully supported by now?);
- IDE sports an hack to not make 512 to 256 sector byte translations.
Apparently a SDIP setting is responsible for this?
- Remove kludge for POR bit in a20_ctrl_w fn;
- I/O:
- HW Dip-switches (where applicable) needs a serious clean-up and naming/position
fixing in some cases;
- Export mouse support to an actual PC9871 device;
- Implement IF-SEGA/98 support (Sega Saturn peripheral compatibility for Windows,
available DOS C snippet clearly shows reading in direct mode, an actual SMPC
sub-device sounds unlikely but possible);
- Incomplete SDIP support:
- SDIP never returns a valid state and returns default values even if machine is
soft resetted. By logic should read-back the already existing state, instead
all machines just returns a "set SDIP" warning message at POST no matter what;
- SDIP bank hookup is different across machines, either unmapped or diverging
implementation wise both in port select and behaviour;
- In theory SDIP can be initialized via a BIOS menu, callable by holding down
HELP key at POST. This actually doesn't work for any machine, is it expected to
have key repeat support? Later BIOSes actually have strings for an extended menu
with 3 or 4 pages strings, may be also requiring a jump/bankswitch to unmapped area?
- Expose SDIP to an actual device_nvram_interface;
- Derive defaults off what the model sets up at POST;
- clean-up functions/variables naming by actual documentation nomenclature;
- derive machine configs & romsets by actual default options, examples:
- 3.5 built-in floppy drives vs. default 5.25;
- separate pc9801f (2DD) available romset to pc9801 (none) & pc9801m (2HD), and
remove the correlated machine config option;
- cbus available number of slots & built-in or provided boards;
- separate machines HDD hooks by SASI/SCSI/IDE;
- load actual IDE bioses from IPL romsets where applicable
(late era 9801 and 9821 class machines);
- pinpoint machines that uses GRCG instead of EGC, we are currently too lenient and support
latter on most (use dbuster and hypbingo to checkout);
- Improve opacity of video flip/flop registers, consider using an address space instead of
current array format;
TODO (PC-9801F)
- it currently hooks up half size kanji ROMs, causing missing text in many games;
TODO (PC-9801RS):
- several unemulated extra f/f features;
- keyboard shift doesn't seem to disable properly (fixed by now?);
- Several games hangs with stuck note by misfired/not catched up -26 / -86 irq;
- clean-up duplicate code;
TODO (PC-9801RX?):
- Identify model type, it clearly accesses PCI, the extended 3'5 floppy I/O at 0x4be and
it's not a 286 CPU;
- Floppy boot fails;
TODO (PC-9801US):
- "Invalid Command Byte 13" for bitmap upd7220 at POST (?)
- "SYSTEM SHUTDOWN" after BIOS sets up the SDIP values;
TODO (PC-9801BX2)
- "SYSTEM SHUTDOWN" at POST, a soft reset fixes it?
- A non-fatal "MEMORY ERROR" is always thrown no matter the RAM size afterwards, related?
- unemulated conventional or EMS RAM bank, definitely should have one given the odd minimum RAM size;
===================================================================================================
This series features a huge number of models released between 1982 and 1997. They
were not IBM PC-compatible, but they had similar hardware (and software: in the
1990s, they run MS Windows as OS)
Models:
| CPU | RAM | Drives | CBus| Release |
PC-9801 | 8086 @ 5 | 128 KB | - | 6 | 1982/10 |
PC-9801F1 | 8086-2 @ 5/8 | 128 KB | 5"2DDx1 | 4 | 1983/10 |
PC-9801F2 | 8086-2 @ 5/8 | 128 KB | 5"2DDx2 | 4 | 1983/10 |
PC-9801E | 8086-2 @ 5/8 | 128 KB | - | 6 | 1983/11 |
PC-9801F3 | 8086-2 @ 5/8 | 256 KB | 5"2DDx1, 10M SASI HDD | 2 | 1984/10 |
PC-9801M2 | 8086-2 @ 5/8 | 256 KB | 5"2HDx2 | 4 | 1984/11 |
PC-9801M3 | 8086-2 @ 5/8 | 256 KB | 5"2HDx1, 20M SASI HDD | 3 | 1985/02 |
PC-9801U2 | V30 @ 8 | 128 KB | 3.5"2HDx2 | 2 | 1985/05 |
PC-98XA1 | 80286 @ 8 | 512 KB | - | 6 | 1985/05 |
PC-98XA2 | 80286 @ 8 | 512 KB | 5"2DD/2HDx2 | 6 | 1985/05 |
PC-98XA3 | 80286 @ 8 | 512 KB | 5"2DD/2HDx1, 20M SASI HDD | 6 | 1985/05 |
PC-9801VF2 | V30 @ 8 | 384 KB | 5"2DDx2 | 4 | 1985/07 |
PC-9801VM0 | V30 @ 8/10 | 384 KB | - | 4 | 1985/07 |
PC-9801VM2 | V30 @ 8/10 | 384 KB | 5"2DD/2HDx2 | 4 | 1985/07 |
PC-9801VM4 | V30 @ 8/10 | 384 KB | 5"2DD/2HDx2, 20M SASI HDD | 4 | 1985/10 |
PC-98XA11 | 80286 @ 8 | 512 KB | - | 6 | 1986/05 |
PC-98XA21 | 80286 @ 8 | 512 KB | 5"2DD/2HDx2 | 6 | 1986/05 |
PC-98XA31 | 80286 @ 8 | 512 KB | 5"2DD/2HDx1, 20M SASI HDD | 6 | 1986/05 |
PC-9801UV2 | V30 @ 8/10 | 384 KB | 3.5"2DD/2HDx2 | 2 | 1986/05 |
PC-98LT1 | V50 @ 8 | 384 KB | 3.5"2DD/2HDx1 | 0 | 1986/11 |
PC-98LT2 | V50 @ 8 | 384 KB | 3.5"2DD/2HDx1 | 0 | 1986/11 |
PC-9801VM21 | V30 @ 8/10 | 640 KB | 5"2DD/2HDx2 | 4 | 1986/11 |
PC-9801VX0 | 80286 @ 8 & V30 @ 8/10 | 640 KB | - | 4 | 1986/11 |
PC-9801VX2 | 80286 @ 8 & V30 @ 8/10 | 640 KB | 5"2DD/2HDx2 | 4 | 1986/11 |
PC-9801VX4 | 80286 @ 8 & V30 @ 8/10 | 640 KB | 5"2DD/2HDx2, 20M SASI HDD | 4 | 1986/11 |
PC-9801VX4/WN | 80286 @ 8 & V30 @ 8/10 | 640 KB | 5"2DD/2HDx2, 20M SASI HDD | 4 | 1986/11 |
PC-98XL1 | 80286 @ 8 & V30 @ 8/10 | 1152 KB | - | 4 | 1986/12 |
PC-98XL2 | 80286 @ 8 & V30 @ 8/10 | 1152 KB | 5"2DD/2HDx2 | 4 | 1986/12 |
PC-98XL4 | 80286 @ 8 & V30 @ 8/10 | 1152 KB | 5"2DD/2HDx1, 20M SASI HDD | 4 | 1986/12 |
PC-9801VX01 | 80286-10 @ 8/10 & V30 @ 8/10 | 640 KB | - | 4 | 1987/06 |
PC-9801VX21 | 80286-10 @ 8/10 & V30 @ 8/10 | 640 KB | 5"2DD/2HDx2 | 4 | 1987/06 |
PC-9801VX41 | 80286-10 @ 8/10 & V30 @ 8/10 | 640 KB | 5"2DD/2HDx2, 20M SASI HDD | 4 | 1987/06 |
PC-9801UV21 | V30 @ 8/10 | 640 KB | 3.5"2DD/2HDx2 | 2 | 1987/06 |
PC-98XL^2 | i386DX-16 @ 16 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2, 40M SASI HDD | 4 | 1987/10 |
PC-98LT11 | V50 @ 8 | 640 KB | 3.5"2DD/2HDx1 | 0 | 1987/10 |
PC-98LT21 | V50 @ 8 | 640 KB | 3.5"2DD/2HDx1 | 0 | 1987/10 |
PC-9801UX21 | 80286-10 @ 10 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2 | 3 | 1987/10 |
PC-9801UX41 | 80286-10 @ 10 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2, 20M SASI HDD | 3 | 1987/10 |
PC-9801LV21 | V30 @ 8/10 | 640 KB | 3.5"2DD/2HDx2 | 0 | 1988/03 |
PC-9801CV21 | V30 @ 8/10 | 640 KB | 3.5"2DD/2HDx2 | 2 | 1988/03 |
PC-9801UV11 | V30 @ 8/10 | 640 KB | 3.5"2DD/2HDx2 | 2 | 1988/03 |
PC-9801RA2 | i386DX-16 @ 16 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2 | 4 | 1988/07 |
PC-9801RA5 | i386DX-16 @ 16 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2, 40M SASI HDD | 4 | 1988/07 |
PC-9801RX2 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 5"2DD/2HDx2 | 4 | 1988/07 |
PC-9801RX4 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 5"2DD/2HDx2, 20M SASI HDD | 4 | 1988/07 |
PC-98LT22 | V50 @ 8 | 640 KB | 3.5"2DD/2HDx1 | 0 | 1988/11 |
PC-98LS2 | i386SX-16 @ 16 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2 | 0 | 1988/11 |
PC-98LS5 | i386SX-16 @ 16 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2, 40M SASI HDD | 0 | 1988/11 |
PC-9801VM11 | V30 @ 8/10 | 640 KB | 5"2DD/2HDx2 | 4 | 1988/11 |
PC-9801LV22 | V30 @ 8/10 | 640 KB | 3.5"2DD/2HDx2 | 0 | 1989/01 |
PC-98RL2 | i386DX-20 @ 16/20 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2 | 4 | 1989/02 |
PC-98RL5 | i386DX-20 @ 16/20 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2, 40M SASI HDD | 4 | 1989/02 |
PC-9801EX2 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2 | 3 | 1989/04 |
PC-9801EX4 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2, 20M SASI HDD | 3 | 1989/04 |
PC-9801ES2 | i386SX-16 @ 16 & V30 @ 8 | 1.6 MB | 3.5"2DD/2HDx2 | 3 | 1989/04 |
PC-9801ES5 | i386SX-16 @ 16 & V30 @ 8 | 1.6 MB | 3.5"2DD/2HDx2, 40M SASI HDD | 3 | 1989/04 |
PC-9801LX2 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2 | 0 | 1989/04 |
PC-9801LX4 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2, 20M SASI HDD | 0 | 1989/04 |
PC-9801LX5 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2, 40M SASI HDD | 0 | 1989/06 |
PC-98DO | V30 @ 8/10 | 640 KB | 5"2DD/2HDx2 | 1 | 1989/06 |
PC-9801LX5C | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2, 40M SASI HDD | 0 | 1989/06 |
PC-9801RX21 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 5"2DD/2HDx2 | 4 | 1989/10 |
PC-9801RX51 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 5"2DD/2HDx2, 40M SASI HDD | 4 | 1989/10 |
PC-9801RA21 | i386DX-20 @ 16/20 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2 | 4 | 1989/11 |
PC-9801RA51 | i386DX-20 @ 16/20 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2, 40M SASI HDD | 4 | 1989/11 |
PC-9801RS21 | i386SX-16 @ 16 & V30 @ 8 | 640 KB | 5"2DD/2HDx2 | 4 | 1989/11 |
PC-9801RS51 | i386SX-16 @ 16 & V30 @ 8 | 640 KB | 5"2DD/2HDx2, 40M SASI HDD | 4 | 1989/11 |
PC-9801N | V30 @ 10 | 640 KB | 3.5"2DD/2HDx1 | 0 | 1989/11 |
PC-9801TW2 | i386SX-20 @ 20 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2 | 2 | 1990/02 |
PC-9801TW5 | i386SX-20 @ 20 & V30 @ 8 | 1.6 MB | 3.5"2DD/2HDx2, 40M SASI HDD | 2 | 1990/02 |
PC-9801TS5 | i386SX-20 @ 20 & V30 @ 8 | 1.6 MB | 3.5"2DD/2HDx2, 40M SASI HDD | 2 | 1990/06 |
PC-9801NS | i386SX-12 @ 12 | 1.6 MB | 3.5"2DD/2HDx1 | 0 | 1990/06 |
PC-9801TF5 | i386SX-20 @ 20 & V30 @ 8 | 1.6 MB | 3.5"2DD/2HDx2, 40M SASI HDD | 2 | 1990/07 |
PC-9801NS-20 | i386SX-12 @ 12 | 1.6 MB | 3.5"2DD/2HDx1, 20M SASI HDD | 0 | 1990/09 |
PC-98RL21 | i386DX-20 @ 20 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2 | 4 | 1990/09 |
PC-98RL51 | i386DX-20 @ 20 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx1, 40M SASI HDD | 4 | 1990/09 |
PC-98DO+ | V33A @ 8/16 | 640 KB | 5"2DD/2HDx2 | 1 | 1990/10 |
PC-9801DX2 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 5"2DD/2HDx2 | 4 | 1990/11 |
PC-9801DX/U2 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2 | 4 | 1990/11 |
PC-9801DX5 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 5"2DD/2HDx2, 40M SASI HDD | 4 | 1990/11 |
PC-9801DX/U5 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2, 40M SASI HDD | 4 | 1990/11 |
PC-9801NV | V30HL @ 8/16 | 1.6 MB | 3.5"2DD/2HDx1 | 0 | 1990/11 |
PC-9801DS2 | i386SX-16 @ 16 & V30 @ 8 | 640 KB | 5"2DD/2HDx2 | 4 | 1991/01 |
PC-9801DS/U2 | i386SX-16 @ 16 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2 | 4 | 1991/01 |
PC-9801DS5 | i386SX-16 @ 16 & V30 @ 8 | 640 KB | 5"2DD/2HDx2, 40M SASI HDD | 4 | 1991/01 |
PC-9801DS/U5 | i386SX-16 @ 16 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2, 40M SASI HDD | 4 | 1991/01 |
PC-9801DA2 | i386DX-20 @ 16/20 & V30 @ 8 | 1.6 MB | 5"2DD/2HDx2 | 4 | 1991/01 |
PC-9801DA/U2 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2 | 4 | 1991/01 |
PC-9801DA5 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 5"2DD/2HDx2, 40M SASI HDD | 4 | 1991/01 |
PC-9801DA/U5 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2, 40M SASI HDD | 4 | 1991/01 |
PC-9801DA7 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 5"2DD/2HDx2, 100M SCSI HDD | 4 | 1991/02 |
PC-9801DA/U7 | 80286-12 @ 10/12 & V30 @ 8 | 640 KB | 3.5"2DD/2HDx2, 100M SCSI HDD | 4 | 1991/02 |
PC-9801UF | V30 @ 8/16 | 640 KB | 3.5"2DD/2HDx2 | 2 | 1991/02 |
PC-9801UR | V30 @ 8/16 | 640 KB | 3.5"2DD/2HDx1, 1.25MB RAM Disk | 2 | 1991/02 |
PC-9801UR/20 | V30 @ 8/16 | 640 KB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 20M SASI HDD | 2 | 1991/02 |
PC-9801NS/E | i386SX-16 @ 16 | 1.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk | 0 | 1991/06 |
PC-9801NS/E20 | i386SX-16 @ 16 | 1.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 20M SASI HDD | 0 | 1991/06 |
PC-9801NS/E40 | i386SX-16 @ 16 | 1.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 40M SASI HDD | 0 | 1991/06 |
PC-9801TW7 | i386SX-20 @ 20 & V30 @ 8 | 1.6 MB | 3.5"2DD/2HDx2, 100M SCSI HDD | 2 | 1991/07 |
PC-9801TF51 | i386SX-20 @ 20 & V30 @ 8 | 1.6 MB | 3.5"2DD/2HDx2, 40M SASI HDD | 2 | 1991/07 |
PC-9801TF71 | i386SX-20 @ 20 & V30 @ 8 | 1.6 MB | 3.5"2DD/2HDx2, 100M SCSI HDD | 2 | 1991/07 |
PC-9801NC | i386SX-20 @ 20 | 2.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk | 0 | 1991/10 |
PC-9801NC40 | i386SX-20 @ 20 | 2.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 40M SASI HDD | 0 | 1991/10 |
PC-9801CS2 | i386SX-16 @ 16 | 640 KB | 3.5"2DD/2HDx2 | 2 | 1991/10 |
PC-9801CS5 | i386SX-16 @ 16 | 640 KB | 3.5"2DD/2HDx2, 40M SASI HDD | 2 | 1991/10 |
PC-9801CS5/W | i386SX-16 @ 16 | 3.6 MB | 3.5"2DD/2HDx2, 40M SASI HDD | 2 | 1991/11 |
PC-98GS1 | i386SX-20 @ 20 & V30 @ 8 | 2.6 MB | 3.5"2DD/2HDx2, 40M SASI HDD | 3 | 1991/11 |
PC-98GS2 | i386SX-20 @ 20 & V30 @ 8 | 2.6 MB | 3.5"2DD/2HDx2, 40M SASI HDD, 1xCD-ROM | 3 | 1991/11 |
PC-9801FA2 | i486SX-16 @ 16 | 1.6 MB | 5"2DD/2HDx2 | 4 | 1992/01 |
PC-9801FA/U2 | i486SX-16 @ 16 | 1.6 MB | 3.5"2DD/2HDx2 | 4 | 1992/01 |
PC-9801FA5 | i486SX-16 @ 16 | 1.6 MB | 5"2DD/2HDx2, 40M SCSI HDD | 4 | 1992/01 |
PC-9801FA/U5 | i486SX-16 @ 16 | 1.6 MB | 3.5"2DD/2HDx2, 40M SCSI HDD | 4 | 1992/01 |
PC-9801FA7 | i486SX-16 @ 16 | 1.6 MB | 5"2DD/2HDx2, 100M SCSI HDD | 4 | 1992/01 |
PC-9801FA/U7 | i486SX-16 @ 16 | 1.6 MB | 3.5"2DD/2HDx2, 100M SCSI HDD | 4 | 1992/01 |
PC-9801FS2 | i386SX-20 @ 16/20 | 1.6 MB | 5"2DD/2HDx2 | 4 | 1992/05 |
PC-9801FS/U2 | i386SX-20 @ 16/20 | 1.6 MB | 3.5"2DD/2HDx2 | 4 | 1992/05 |
PC-9801FS5 | i386SX-20 @ 16/20 | 1.6 MB | 5"2DD/2HDx2, 40M SCSI HDD | 4 | 1992/05 |
PC-9801FS/U5 | i386SX-20 @ 16/20 | 1.6 MB | 3.5"2DD/2HDx2, 40M SCSI HDD | 4 | 1992/05 |
PC-9801FS7 | i386SX-20 @ 16/20 | 1.6 MB | 5"2DD/2HDx2, 100M SCSI HDD | 4 | 1992/01 |
PC-9801FS/U7 | i386SX-20 @ 16/20 | 1.6 MB | 3.5"2DD/2HDx2, 100M SCSI HDD | 4 | 1992/01 |
PC-9801NS/T | i386SL(98) @ 20 | 1.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk | 0 | 1992/01 |
PC-9801NS/T40 | i386SL(98) @ 20 | 1.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 40M SASI HDD | 0 | 1992/01 |
PC-9801NS/T80 | i386SL(98) @ 20 | 1.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 80M SASI HDD | 0 | 1992/01 |
PC-9801NL | V30H @ 8/16 | 640 KB | 1.25 MB RAM Disk | 0 | 1992/01 |
PC-9801FX2 | i386SX-12 @ 10/12 | 1.6 MB | 5"2DD/2HDx2 | 4 | 1992/05 |
PC-9801FX/U2 | i386SX-12 @ 10/12 | 1.6 MB | 3.5"2DD/2HDx2 | 4 | 1992/05 |
PC-9801FX5 | i386SX-12 @ 10/12 | 1.6 MB | 5"2DD/2HDx2, 40M SCSI HDD | 4 | 1992/05 |
PC-9801FX/U5 | i386SX-12 @ 10/12 | 1.6 MB | 3.5"2DD/2HDx2, 40M SCSI HDD | 4 | 1992/05 |
PC-9801US | i386SX-16 @ 16 | 1.6 MB | 3.5"2DD/2HDx2 | 2 | 1992/07 |
PC-9801US40 | i386SX-16 @ 16 | 1.6 MB | 3.5"2DD/2HDx2, 40M SASI HDD | 2 | 1992/07 |
PC-9801US80 | i386SX-16 @ 16 | 1.6 MB | 3.5"2DD/2HDx2, 80M SASI HDD | 2 | 1992/07 |
PC-9801NS/L | i386SX-20 @ 10/20 | 1.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk | 0 | 1992/07 |
PC-9801NS/L40 | i386SX-20 @ 10/20 | 1.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 40M SASI HDD | 0 | 1992/07 |
PC-9801NA | i486SX-20 @ 20 | 2.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk | 0 | 1992/11 |
PC-9801NA40 | i486SX-20 @ 20 | 2.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 40M SASI HDD | 0 | 1992/11 |
PC-9801NA120 | i486SX-20 @ 20 | 2.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 120M SASI HDD | 0 | 1992/11 |
PC-9801NA/C | i486SX-20 @ 20 | 2.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk | 0 | 1992/11 |
PC-9801NA40/C | i486SX-20 @ 20 | 2.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 40M SASI HDD | 0 | 1992/11 |
PC-9801NA120/C | i486SX-20 @ 20 | 2.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk, 120M SASI HDD | 0 | 1992/11 |
PC-9801NS/R | i486SX(J) @ 20 | 1.6 MB | 3.5"2DD/2HDx1 (3mode), 1.25MB RAM Disk | 0 | 1993/01 |
PC-9801NS/R40 | i486SX(J) @ 20 | 1.6 MB | 3.5"2DD/2HDx1 (3mode), 1.25MB RAM Disk, 40M SASI HDD | 0 | 1993/01 |
PC-9801NS/R120 | i486SX(J) @ 20 | 1.6 MB | 3.5"2DD/2HDx1 (3mode), 1.25MB RAM Disk, 120M SASI HDD | 0 | 1993/01 |
PC-9801BA/U2 | i486DX2-40 @ 40 | 1.6 MB | 3.5"2DD/2HDx2 | 3 | 1993/01 |
PC-9801BA/U6 | i486DX2-40 @ 40 | 3.6 MB | 3.5"2DD/2HDx1, 40M SASI HDD | 3 | 1993/01 |
PC-9801BA/M2 | i486DX2-40 @ 40 | 1.6 MB | 5"2DD/2HDx2 | 3 | 1993/01 |
PC-9801BX/U2 | i486SX-20 @ 20 | 1.6 MB | 3.5"2DD/2HDx2 | 3 | 1993/01 |
PC-9801BX/U6 | i486SX-20 @ 20 | 3.6 MB | 3.5"2DD/2HDx1, 40M SASI HDD | 3 | 1993/01 |
PC-9801BX/M2 | i486SX-20 @ 20 | 1.6 MB | 5"2DD/2HDx2 | 3 | 1993/01 |
PC-9801NX/C | i486SX(J) @ 20 | 1.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk | 0 | 1993/07 |
PC-9801NX/C120 | i486SX(J) @ 20 | 3.6 MB | 3.5"2DD/2HDx1, 1.25MB RAM Disk | 0 | 1993/07 |
PC-9801P40/D | i486SX(J) @ 20 | 5.6 MB | 40MB IDE HDD | 0 | 1993/07 |
PC-9801P80/W | i486SX(J) @ 20 | 7.6 MB | 80MB IDE HDD | 0 | 1993/07 |
PC-9801P80/P | i486SX(J) @ 20 | 7.6 MB | 80MB IDE HDD | 0 | 1993/07 |
PC-9801BA2/U2 | i486DX2-66 @ 66 | 3.6 MB | 3.5"2DD/2HDx2 | 3 | 1993/11 |
PC-9801BA2/U7 | i486DX2-66 @ 66 | 3.6 MB | 3.5"2DD/2HDx1, 120MB IDE HDD | 3 | 1993/11 |
PC-9801BA2/M2 | i486DX2-66 @ 66 | 3.6 MB | 5"2DD/2HDx2 | 3 | 1993/11 |
PC-9801BS2/U2 | i486SX-33 @ 33 | 3.6 MB | 3.5"2DD/2HDx2 | 3 | 1993/11 |
PC-9801BS2/U7 | i486SX-33 @ 33 | 3.6 MB | 3.5"2DD/2HDx1, 120MB IDE HDD | 3 | 1993/11 |
PC-9801BS2/M2 | i486SX-33 @ 33 | 3.6 MB | 5"2DD/2HDx2 | 3 | 1993/11 |
PC-9801BX2/U2 | i486SX-25 @ 25 | 1.8 MB | 3.5"2DD/2HDx2 | 3 | 1993/11 |
PC-9801BX2/U7 | i486SX-25 @ 25 | 3.6 MB | 3.5"2DD/2HDx1, 120MB IDE HDD | 3 | 1993/11 |
PC-9801BX2/M2 | i486SX-25 @ 25 | 1.8 MB | 5"2DD/2HDx2 | 3 | 1993/11 |
PC-9801BA3/U2 | i486DX-66 @ 66 | 3.6 MB | 3.5"2DD/2HDx2 | 3 | 1995/01 |
PC-9801BA3/U2/W | i486DX-66 @ 66 | 7.6 MB | 3.5"2DD/2HDx2, 210MB IDE HDD | 3 | 1995/01 |
PC-9801BX3/U2 | i486SX-33 @ 33 | 1.6 MB | 3.5"2DD/2HDx2 | 3 | 1995/01 |
PC-9801BX3/U2/W | i486SX-33 @ 33 | 5.6 MB | 3.5"2DD/2HDx2, 210MB IDE HDD | 3 | 1995/01 |
PC-9801BX4/U2 | AMD/i 486DX2-66 @ 66 | 2 MB | 3.5"2DD/2HDx2 | 3 | 1995/07 |
PC-9801BX4/U2/C | AMD/i 486DX2-66 @ 66 | 2 MB | 3.5"2DD/2HDx2, 2xCD-ROM | 3 | 1995/07 |
PC-9801BX4/U2-P | Pentium ODP @ 66 | 2 MB | 3.5"2DD/2HDx2 | 3 | 1995/09 |
PC-9801BX4/U2/C-P | Pentium ODP @ 66 | 2 MB | 3.5"2DD/2HDx2, 2xCD-ROM | 3 | 1995/09 |
For more info (e.g. optional hardware), see http://www.geocities.jp/retro_zzz/machines/nec/9801/mdl98cpu.html
PC-9821 Series
PC-9821 (1992) - aka 98MULTi, desktop computer, 386 based
PC-9821A series (1993->1994) - aka 98MATE A, desktop computers, 486 based
PC-9821B series (1993) - aka 98MATE B, desktop computers, 486 based
PC-9821C series (1993->1996) - aka 98MULTi CanBe, desktop & tower computers, various CPU
PC-9821Es (1994) - aka 98FINE, desktop computer with integrated LCD, successor of the PC-98T
PC-9821X series (1994->1995) - aka 98MATE X, desktop computers, Pentium based
PC-9821V series (1995) - aka 98MATE Valuestar, desktop computers, Pentium based
PC-9821S series (1995->1996) - aka 98Pro, tower computers, PentiumPro based
PC-9821R series (1996->2000) - aka 98MATE R, desktop & tower & server computers, various CPU
PC-9821C200 (1997) - aka CEREB, desktop computer, Pentium MMX based
PC-9821 Ne/Ns/Np/Nm (1993->1995) - aka 98NOTE, laptops, 486 based
PC-9821 Na/Nb/Nw (1995->1997) - aka 98NOTE Lavie, laptops, Pentium based
PC-9821 Lt/Ld (1995) - aka 98NOTE Light, laptops, 486 based
PC-9821 La/Ls (1995->1997) - aka 98NOTE Aile, laptops, Pentium based
====
Documentation notes (for unemulated stuff, courtesy of T. Kodaka and T. Kono):
IDE:
(r/w)
0x430: IDE drive switch
0x432: IDE drive switch
0x435: <unknown>
(ISA correlated i/o)
----------------------------------------------------------
0x0640 |WORD|R/W|Data Register |01F0h
0x0642 |BYTE| R |Error Register |01F1h
0x0642 |BYTE| W |Write Precomp Register |01F1h
0x0644 |BYTE|R/W|Sector Count |01F2h
0x0646 |BYTE|R/W|Sector Number |01F3h
0x0648 |BYTE|R/W|Cylinder Low |01F4h
0x064A |BYTE|R/W|Cylinder High |01F5h
0x064C |BYTE|R/W|SDH Register |01F6h
0x064E |BYTE| R |Status Register |01F7h
0x064E |BYTE| W |Command Register |01F7h
0x074C |BYTE| R |Alternate Status Register |03F6h
0x074C |BYTE| W |Digital Output Register |03F6h
0x074E |BYTE| R |Digital Input Register |03F7h
Video F/F (i/o 0x68):
KAC mode (video ff = 5) is basically how the kanji ROM could be accessed, 1=thru the CG window ports, 0=thru the kanji
window RAM at 0xa4***.
My guess is that the system locks up or doesn't have any data if the wrong port is being accessed.
Ext Video F/F (i/o 0x6a):
0000 011x enables EGC
0000 111x enables PC-98GS
0010 000x enables multicolor (a.k.a. 256 colors mode)
0010 001x enables 65'536 colors
0010 010x 64k color palette related (?)
0010 011x full screen reverse (?)
0010 100x text and gfxs synthesis (?)
0010 101x 256 color palette registers fast write (?)
0010 110x 256 color overscan (?)
0100 000x (0) CRT (1) Plasma/LCD
0100 001x text and gfxs right shifted one dot (undocumented behaviour)
0100 010x hi-res mode in PC-9821
0110 000x EEGC mode
0110 001x VRAM config (0) plain (1) packed
0110 011x AGDC mode
0110 100x 480 lines
0110 110x VRAM bitmap orientation (0) MSB left-to-right LSB (1) LSB left-to-right MSB
1000 001x CHR GDC clock (0) 2,5 MHz (1) 5 MHz
1000 010x BMP GDC clock
1000 111x related to GFX accelerator cards (like Vision864)
1100 010x chart GDC operating mode (?)
(everything else is undocumented / unknown)
Keyboard TX commands:
0xfa ACK
0xfc NACK
0x95
---- --xx extension key settings (00 normal 11 Win and App Keys enabled)
0x96 identification codes
0x9c
-xx- ---- key delay (11 = 1000 ms, 10 = 500 ms, 01 = 500 ms, 00 = 250 ms)
---x xxxx repeat rate (slow 11111 -> 00001 fast)
0x9d keyboard LED settings
0x9f keyboard ID
**************************************************************************************************/
#include "emu.h"
#include "pc9801.h"
#include "machine/input_merger.h"
void pc98_base_state::rtc_w(uint8_t data)
{
m_rtc->c0_w(BIT(data, 0));
m_rtc->c1_w(BIT(data, 1));
m_rtc->c2_w(BIT(data, 2));
m_rtc->stb_w(BIT(data, 3));
m_rtc->clk_w(BIT(data, 4));
m_rtc->data_in_w(BIT(data, 5));
if(data & 0xc0)
logerror("RTC write to undefined bits %02x\n",data & 0xc0);
}
void pc9801_state::dmapg4_w(offs_t offset, uint8_t data)
{
if(offset < 4)
m_dma_offset[(offset+1) & 3] = data & 0x0f;
}
void pc9801vm_state::dmapg8_w(offs_t offset, uint8_t data)
{
if(offset == 4)
m_dma_autoinc[data & 3] = (data >> 2) & 3;
else if(offset < 4)
m_dma_offset[(offset+1) & 3] = data;
}
void pc9801_state::nmi_ctrl_w(offs_t offset, uint8_t data)
{
m_nmi_ff = offset;
}
void pc9801_state::vrtc_clear_w(uint8_t data)
{
m_pic1->ir2_w(0);
}
u8 pc9801_state::fdc_2hd_ctrl_r()
{
return 0x44;
}
void pc9801_state::fdc_2hd_ctrl_w(u8 data)
{
//logerror("%02x ctrl\n",data);
m_fdc_2hd->reset_w(BIT(data, 7));
m_fdc_2hd_ctrl = data;
if(data & 0x40)
{
m_fdc_2hd->set_ready_line_connected(0);
m_fdc_2hd->ready_w(0);
}
else
m_fdc_2hd->set_ready_line_connected(1);
if(!m_sys_type) // required for 9801f 2hd adapter bios
{
m_fdc_2hd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? ASSERT_LINE : CLEAR_LINE);
m_fdc_2hd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? ASSERT_LINE : CLEAR_LINE);
}
}
bool pc9801_state::fdc_drive_ready_r(upd765a_device *fdc)
{
floppy_image_device *floppy0 = fdc->subdevice<floppy_connector>("0")->get_device();
floppy_image_device *floppy1 = fdc->subdevice<floppy_connector>("1")->get_device();
return (!floppy0->ready_r() || !floppy1->ready_r());
}
uint8_t pc9801_state::fdc_2dd_ctrl_r()
{
u8 ret = 0;
// 2dd BIOS specifically tests if a disk is in any drive
// (does not happen on 2HD standalone)
ret |= fdc_drive_ready_r(m_fdc_2dd) << 4;
//popmessage("%d %d %02x", floppy0->ready_r(), floppy1->ready_r(), ret);
// TODO: dips et al.
return ret | 0x40;
}
void pc9801_state::fdc_2dd_ctrl_w(uint8_t data)
{
logerror("%02x ctrl\n",data);
m_fdc_2dd->reset_w(BIT(data, 7));
m_fdc_2dd_ctrl = data;
m_fdc_2dd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
m_fdc_2dd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
}
u8 pc9801vm_state::ide_ctrl_r()
{
address_space &ram = m_maincpu->space(AS_PROGRAM);
// this makes the ide driver not do 512 to 256 byte sector translation, the 9821 looks for bit 6 of offset 0xac403 of the kanji ram to set this, the rs unknown
ram.write_byte(0x457, ram.read_byte(0x457) | 0xc0);
return m_ide_sel;
}
void pc9801vm_state::ide_ctrl_w(u8 data)
{
if(!(data & 0x80))
m_ide_sel = data & 1;
}
uint16_t pc9801vm_state::ide_cs0_r(offs_t offset, uint16_t mem_mask)
{
return m_ide[m_ide_sel]->cs0_r(offset, mem_mask);
}
void pc9801vm_state::ide_cs0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
m_ide[m_ide_sel]->cs0_w(offset, data, mem_mask);
}
uint16_t pc9801vm_state::ide_cs1_r(offs_t offset, uint16_t mem_mask)
{
return m_ide[m_ide_sel]->cs1_r(offset, mem_mask);
}
void pc9801vm_state::ide_cs1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
m_ide[m_ide_sel]->cs1_w(offset, data, mem_mask);
}
uint8_t pc9801_state::sasi_data_r()
{
uint8_t data = m_sasi_data_in->read();
if(m_sasi_ctrl_in->read() & 0x80)
m_sasibus->write_ack(1);
return data;
}
void pc9801_state::sasi_data_w(uint8_t data)
{
m_sasi_data = data;
if (m_sasi_data_enable)
{
m_sasi_data_out->write(m_sasi_data);
if(m_sasi_ctrl_in->read() & 0x80)
m_sasibus->write_ack(1);
}
}
void pc9801_state::write_sasi_io(int state)
{
m_sasi_ctrl_in->write_bit2(state);
m_sasi_data_enable = !state;
if (m_sasi_data_enable)
{
m_sasi_data_out->write(m_sasi_data);
}
else
{
m_sasi_data_out->write(0);
}
if((m_sasi_ctrl_in->read() & 0x9c) == 0x8c)
m_pic2->ir1_w(m_sasi_ctrl & 1);
else
m_pic2->ir1_w(0);
}
void pc9801_state::write_sasi_req(int state)
{
m_sasi_ctrl_in->write_bit7(state);
if (!state)
m_sasibus->write_ack(0);
if((m_sasi_ctrl_in->read() & 0x9C) == 0x8C)
m_pic2->ir1_w(m_sasi_ctrl & 1);
else
m_pic2->ir1_w(0);
m_dmac->dreq0_w(!(state && !(m_sasi_ctrl_in->read() & 8) && (m_sasi_ctrl & 2)));
}
uint8_t pc9801_state::sasi_status_r()
{
uint8_t res = 0;
if(m_sasi_ctrl & 0x40) // read status
{
/*
x--- ---- REQ
-x-- ---- ACK
--x- ---- BSY
---x ---- MSG
---- x--- CD
---- -x-- IO
---- ---x INT?
*/
res |= m_sasi_ctrl_in->read();
}
else // read drive info
{
/*
xx-- ---- unknown but tested
--xx x--- SASI-1 media type
---- -xxx SASI-2 media type
*/
//res |= 7 << 3; // read mediatype SASI-1
//res |= 7; // read mediatype SASI-2
}
return res;
}
void pc9801_state::sasi_ctrl_w(uint8_t data)
{
/*
x--- ---- channel enable
-x-- ---- read switch
--x- ---- sel
---- x--- reset line
---- --x- dma enable
---- ---x irq enable
*/
m_sasibus->write_sel(BIT(data, 5));
if(m_sasi_ctrl & 8 && ((data & 8) == 0)) // 1 -> 0 transition
{
m_sasibus->write_rst(1);
// m_timer_rst->adjust(attotime::from_nsec(100));
}
else
m_sasibus->write_rst(0); // TODO
m_sasi_ctrl = data;
// m_sasibus->write_sel(BIT(data, 0));
}
uint8_t pc9801_state::f0_r(offs_t offset)
{
if(offset == 0)
{
// iterate thru all devices to check if an AMD98 is present
// TODO: move to cbus
for (pc9801_amd98_device &amd98 : device_type_enumerator<pc9801_amd98_device>(machine().root_device()))
{
logerror("%s: Read AMD98 ID %s\n", machine().describe_context(), amd98.tag());
return 0x18; // return the right ID
}
logerror("%s: Read port 0 from 0xf0 (AMD98 check?)\n", machine().describe_context());
return 0; // card not present
}
return 0xff;
}
void pc9801_state::pc9801_map(address_map &map)
{
map(0xa0000, 0xa3fff).rw(FUNC(pc9801_state::tvram_r), FUNC(pc9801_state::tvram_w)); //TVRAM
map(0xa8000, 0xbffff).rw(FUNC(pc9801_state::gvram_r), FUNC(pc9801_state::gvram_w)); //bitmap VRAM
// map(0xcc000, 0xcffff).rom().region("sound_bios", 0); //sound BIOS
map(0xd6000, 0xd6fff).rom().region("fdc_bios_2dd", 0); //floppy BIOS 2dd
map(0xd7000, 0xd7fff).rom().region("fdc_bios_2hd", 0); //floppy BIOS 2hd
map(0xe8000, 0xfffff).rom().region("ipl", 0);
}
/* first device is even offsets, second one is odd offsets */
void pc9801_state::pc9801_common_io(address_map &map)
{
// map.unmap_value_high();
map(0x0000, 0x001f).rw(m_dmac, FUNC(am9517a_device::read), FUNC(am9517a_device::write)).umask16(0xff00);
map(0x0000, 0x001f).rw(FUNC(pc9801_state::pic_r), FUNC(pc9801_state::pic_w)).umask16(0x00ff); // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
map(0x0020, 0x002f).w(FUNC(pc9801_state::rtc_w)).umask16(0x00ff);
map(0x0030, 0x0037).rw(m_ppi_sys, FUNC(i8255_device::read), FUNC(i8255_device::write)).umask16(0xff00);
map(0x0030, 0x0033).rw(m_sio, FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0x00ff); //i8251 RS232c / i8255 system port
map(0x0040, 0x0047).rw(m_ppi_prn, FUNC(i8255_device::read), FUNC(i8255_device::write)).umask16(0x00ff);
map(0x0040, 0x0047).rw(m_keyb, FUNC(pc9801_kbd_device::rx_r), FUNC(pc9801_kbd_device::tx_w)).umask16(0xff00); //i8255 printer port / i8251 keyboard
map(0x0050, 0x0057).lr8(NAME([] (offs_t offset) { return 0xff; })).umask16(0xff00);
map(0x0050, 0x0053).w(FUNC(pc9801_state::nmi_ctrl_w)).umask16(0x00ff); // NMI FF / host FDD 2d (PC-80S31K)
map(0x0060, 0x0063).rw(m_hgdc[0], FUNC(upd7220_device::read), FUNC(upd7220_device::write)).umask16(0x00ff); //upd7220 character ports / <undefined>
map(0x0064, 0x0064).w(FUNC(pc9801_state::vrtc_clear_w));
// map(0x006c, 0x006f) border color / <undefined>
// TODO: PC-98Bible suggests that $73 timer #1 is unavailable on non-vanilla models (verify on HW)
// (can be accessed only thru the $3fdb alias)
map(0x0070, 0x0077).rw(m_pit, FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0xff00);
map(0x0070, 0x007f).rw(FUNC(pc9801_state::txt_scrl_r), FUNC(pc9801_state::txt_scrl_w)).umask16(0x00ff); //display registers / i8253 pit
// map(0x0090, 0x0093).rw(m_sio, FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0xff00); // CMT SIO (optional, C-Bus)
map(0x7fd8, 0x7fdf).rw(m_ppi_mouse, FUNC(i8255_device::read), FUNC(i8255_device::write)).umask16(0xff00);
}
void pc9801_state::pc9801_io(address_map &map)
{
pc9801_common_io(map);
map(0x0020, 0x002f).w(FUNC(pc9801_state::dmapg4_w)).umask16(0xff00);
map(0x0068, 0x0068).w(FUNC(pc9801_state::pc9801_video_ff_w)); //mode FF / <undefined>
map(0x0080, 0x0080).rw(FUNC(pc9801_state::sasi_data_r), FUNC(pc9801_state::sasi_data_w));
map(0x0082, 0x0082).rw(FUNC(pc9801_state::sasi_status_r), FUNC(pc9801_state::sasi_ctrl_w));
map(0x0090, 0x0090).r(m_fdc_2hd, FUNC(upd765a_device::msr_r));
map(0x0092, 0x0092).rw(m_fdc_2hd, FUNC(upd765a_device::fifo_r), FUNC(upd765a_device::fifo_w));
map(0x0094, 0x0094).rw(FUNC(pc9801_state::fdc_2hd_ctrl_r), FUNC(pc9801_state::fdc_2hd_ctrl_w));
map(0x00a0, 0x00af).rw(FUNC(pc9801_state::pc9801_a0_r), FUNC(pc9801_state::pc9801_a0_w)); //upd7220 bitmap ports / display registers
map(0x00c8, 0x00cb).m(m_fdc_2dd, FUNC(upd765a_device::map)).umask16(0x00ff);
map(0x00cc, 0x00cc).rw(FUNC(pc9801_state::fdc_2dd_ctrl_r), FUNC(pc9801_state::fdc_2dd_ctrl_w)); //upd765a 2dd / <undefined>
map(0x00f0, 0x00ff).r(FUNC(pc9801_state::f0_r)).umask16(0x00ff);
}
/*************************************
*
* PC-9801RS specific handlers (IA-32)
*
************************************/
// TODO: it's possible that the offset calculation is actually linear.
// TODO: having this non-linear makes the system to boot in BASIC for PC-9821. Perhaps it stores settings? How to change these?
uint8_t pc9801vm_state::pc9801rs_knjram_r(offs_t offset)
{
uint32_t pcg_offset;
pcg_offset = (m_font_addr & 0x7fff) << 5;
pcg_offset|= offset & 0x1e;
pcg_offset|= m_font_lr;
if(!(m_font_addr & 0xff))
{
int char_size = m_video_ff[FONTSEL_REG];
return m_char_rom[(m_font_addr >> 8) * (8 << char_size) + (char_size * 0x800) + ((offset >> 1) & 0xf)];
}
if((m_font_addr & 0xff00) == 0x5600 || (m_font_addr & 0xff00) == 0x5700)
return m_kanji_rom[pcg_offset];
// TODO: do we really need to recalculate?
pcg_offset = (m_font_addr & 0x7fff) << 5;
pcg_offset|= (offset & 0x1e);
// telenetm defintely needs this for 8x16 romaji title songs, otherwise it blanks them out
// (pc9801vm never reads this area btw)
pcg_offset|= (offset & m_font_lr) & 1;
// pcg_offset|= (m_font_lr);
return m_kanji_rom[pcg_offset];
}
void pc9801vm_state::pc9801rs_knjram_w(offs_t offset, uint8_t data)
{
uint32_t pcg_offset;
pcg_offset = (m_font_addr & 0x7fff) << 5;
pcg_offset|= offset & 0x1e;
pcg_offset|= m_font_lr;
if((m_font_addr & 0xff00) == 0x5600 || (m_font_addr & 0xff00) == 0x5700)
{
m_kanji_rom[pcg_offset] = data;
m_gfxdecode->gfx(2)->mark_dirty(pcg_offset >> 5);
}
}
void pc9801vm_state::pc9801rs_bank_w(offs_t offset, uint8_t data)
{
if(offset == 1)
{
if((data & 0xf0) == 0x00 || (data & 0xf0) == 0x10)
{
if((data & 0xed) == 0x00)
{
m_ipl->set_bank((data & 2) >> 1);
return;
}
}
logerror("Unknown EMS ROM setting %02x\n",data);
}
if(offset == 3)
{
if((data & 0xf0) == 0x20)
m_vram_bank = (data & 2) >> 1;
else
{
logerror("Unknown EMS RAM setting %02x\n",data);
}
}
}
uint8_t pc9801vm_state::a20_ctrl_r(offs_t offset)
{
if(offset == 0x01)
return (m_gate_a20 ^ 1) | 0xfe;
else if(offset == 0x03)
return (m_gate_a20 ^ 1) | (m_nmi_ff << 1);
return f0_r(offset);
}
void pc9801vm_state::a20_ctrl_w(offs_t offset, uint8_t data)
{
if(offset == 0x00)
{
uint8_t por;
/* reset POR bit */
// TODO: is there any other way that doesn't involve direct r/w of ppi address?
por = m_ppi_sys->read(2) & ~0x20;
m_ppi_sys->write(2, por);
m_maincpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
m_gate_a20 = 0;
}
if(offset == 0x01)
m_gate_a20 = 1;
if(offset == 0x03)
{
if(data == 0x02)
m_gate_a20 = 1;
else if(data == 0x03)
m_gate_a20 = 0;
}
m_maincpu->set_input_line(INPUT_LINE_A20, m_gate_a20);
}
uint8_t pc9801_state::grcg_r(offs_t offset)
{
if(offset == 6)
{
logerror("GRCG mode R\n");
return 0xff;
}
else if(offset == 7)
{
logerror("GRCG tile R\n");
return 0xff;
}
return txt_scrl_r(offset);
}
void pc9801_state::grcg_w(offs_t offset, uint8_t data)
{
if(offset == 6)
{
// logerror("%02x GRCG MODE\n",data);
m_grcg.mode = data;
m_grcg.tile_index = 0;
return;
}
else if(offset == 7)
{
// logerror("%02x GRCG TILE %02x\n",data,m_grcg.tile_index);
m_grcg.tile[m_grcg.tile_index] = bitswap<8>(data,0,1,2,3,4,5,6,7);
m_grcg.tile_index ++;
m_grcg.tile_index &= 3;
return;
}
txt_scrl_w(offset,data);
}
void pc9801vm_state::pc9801rs_a0_w(offs_t offset, uint8_t data)
{
if((offset & 1) == 0 && offset & 8 && m_ex_video_ff[ANALOG_16_MODE])
{
switch(offset)
{
case 0x08: m_analog16.pal_entry = data & 0xf; break;
case 0x0a: m_analog16.g[m_analog16.pal_entry] = data & 0xf; break;
case 0x0c: m_analog16.r[m_analog16.pal_entry] = data & 0xf; break;
case 0x0e: m_analog16.b[m_analog16.pal_entry] = data & 0xf; break;
}
m_palette->set_pen_color(
m_analog16.pal_entry + 0x10,
pal4bit(m_analog16.r[m_analog16.pal_entry]),
pal4bit(m_analog16.g[m_analog16.pal_entry]),
pal4bit(m_analog16.b[m_analog16.pal_entry])
);
return;
}
pc9801_a0_w(offset,data);
}
void pc9801vm_state::egc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if(!(m_egc.regs[1] & 0x6000) || (offset != 4)) // why?
COMBINE_DATA(&m_egc.regs[offset]);
switch(offset)
{
case 6:
case 7:
m_egc.count = (m_egc.regs[7] & 0xfff) + 1;
m_egc.first = true;
m_egc.init = false;
break;
}
}
uint16_t pc9801vm_state::grcg_gvram_r(offs_t offset, uint16_t mem_mask)
{
uint16_t ret = upd7220_grcg_r((offset + 0x4000) | (m_vram_bank << 16), mem_mask);
return bitswap<16>(ret,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7);
}
void pc9801vm_state::grcg_gvram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
data = bitswap<16>(data,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7);
upd7220_grcg_w((offset + 0x4000) | (m_vram_bank << 16), data, mem_mask);
}
uint16_t pc9801vm_state::grcg_gvram0_r(offs_t offset, uint16_t mem_mask)
{
uint16_t ret = upd7220_grcg_r(offset | (m_vram_bank << 16), mem_mask);
return bitswap<16>(ret,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7);
}
void pc9801vm_state::grcg_gvram0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
data = bitswap<16>(data,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7);
upd7220_grcg_w(offset | (m_vram_bank << 16), data, mem_mask);
}
/*
* FDC MODE control
*
* ???? ---- <undefined>
* ---- x--- (r/o) DIP-SW 3-2 built-in FDC spec (1) OFF 2HD (0) ON 2DD
* ---- -x-- (r) DIP-SW 3-1 FDC FIXed mode (1) ON
* (w) Enable motor ON (1) defined by 0x94 bit 3 (0) always on
* ---- --x- (r/w) FDD EXC access mode status (1) 2HD (0) 2DD
* ---- ---x (r/w) PORT EXC I/F mode select (1) 2HD (0) 2DD
* (Disables I/O port access)
*
* NB: high-reso class diverges here:
* - XA/XL themselves have no way to access any of this;
* - post-XA/XL just has Enable motor ON writes;
*/
uint8_t pc9801vm_state::fdc_mode_r()
{
return (m_fdc_mode & 3) | 0xf0 | (m_dsw3->read() & 3) << 2;
}
void pc9801vm_state::fdc_set_density_mode(bool is_2hd)
{
floppy_image_device *floppy0 = m_fdc_2hd->subdevice<floppy_connector>("0")->get_device();
floppy_image_device *floppy1 = m_fdc_2hd->subdevice<floppy_connector>("1")->get_device();
floppy0->set_rpm(is_2hd ? 360 : 300);
floppy1->set_rpm(is_2hd ? 360 : 300);
m_fdc_2hd->set_rate(is_2hd ? 500000 : 250000);
// printf("FDC set new mode %s\n", is_2hd ? "2HD" : "2DD");
logerror("%s: FDC set new mode %s\n", machine().describe_context(), is_2hd ? "2HD" : "2DD");
}
void pc9801vm_state::fdc_mode_w(uint8_t data)
{
const bool old_mode = bool(BIT(m_fdc_mode, 1));
const bool new_mode = bool(BIT(data, 1));
if (old_mode != new_mode)
fdc_set_density_mode(new_mode);
m_fdc_mode = data;
if(BIT(m_fdc_mode, 2))
{
m_fdc_2hd->subdevice<floppy_connector>("0")->get_device()->mon_w(CLEAR_LINE);
m_fdc_2hd->subdevice<floppy_connector>("1")->get_device()->mon_w(CLEAR_LINE);
}
//if(data & 0xfc)
// logerror("FDC ctrl called with %02x\n",data);
}
// TODO: undefined/disallow read/writes if I/F mode doesn't match
// (and that applies to FDC mapping too!)
// id port 0 -> 2DD
// id port 1 -> 2HD
template <unsigned port> u8 pc9801vm_state::fdc_2hd_2dd_ctrl_r()
{
u8 res = fdc_2hd_ctrl_r();
if (port == 0)
{
res |= 0x20;
res |= fdc_drive_ready_r(m_fdc_2hd) << 4;
}
return res;
}
TIMER_CALLBACK_MEMBER(pc9801vm_state::fdc_trigger)
{
// TODO: sorcer definitely expects this irq to be taken
if (BIT(m_fdc_2hd_ctrl, 2))
{
m_pic2->ir2_w(0);
m_pic2->ir2_w(1);
}
}
template <unsigned port> void pc9801vm_state::fdc_2hd_2dd_ctrl_w(u8 data)
{
bool prev_trig = false;
bool cur_trig = false;
if (port == 0 && bool(BIT(m_fdc_mode, 0)) == false)
{
prev_trig = bool(BIT(m_fdc_2hd_ctrl, 0));
cur_trig = bool(BIT(data, 0));
}
fdc_2hd_ctrl_w(data);
// TODO: Enable motor ON is reversed compared to the docs
if(!(m_fdc_mode & 4)) // required for 9821
{
m_fdc_2hd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
m_fdc_2hd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
}
if (port == 0 && !prev_trig && cur_trig)
{
m_fdc_timer->reset();
m_fdc_timer->adjust(attotime::from_msec(100));
}
}
void pc9801vm_state::pc9801rs_video_ff_w(offs_t offset, uint8_t data)
{
if(offset == 1)
{
if((data & 0xf0) == 0) /* disable any PC-9821 specific HW regs */
m_ex_video_ff[(data & 0xfe) >> 1] = data & 1;
if(0)
{
static const char *const ex_video_ff_regnames[] =
{
"16 colors mode", // 0
"<unknown>", // 1