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system1.cpp
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system1.cpp
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// license:BSD-3-Clause
// copyright-holders:Jarek Parchanski, Nicola Salmoria, Mirko Buffoni
/******************************************************************************
Sega System 1 / System 2
driver by Jarek Parchanski, Nicola Salmoria, Mirko Buffoni
Up'n Down, Mister Viking, Flicky, SWAT, Water Match and Bull Fight are known
to run on IDENTICAL hardware (they were sold by Bally-Midway as ROM swaps).
DIP locations verified from manual for:
- wboy
- choplift
TODO: - fully understand nobb ports involved in the protection
- different XTAL/divider configurations for some Star Jacker
cabinets? See you.tube/-a7srHVPb_U
*******************************************************************************
Main Snd Gfx1 Gfx2 Max Min
Game ROMs ROMs ROMs ROMs Pal? Intf EPR# EPR#
----------- ----- ----- ----- ----- ---- ---- ---- ----
starjack 6x8k 1x8k 6x8k 2x16k no ppi 5325(b) 5318
starjacks 6x8k 1x8k 6x8k 2x16k no ppi license
upndown 6x8k 1x8k 6x8k 2x16k no ppi 5521 5514
upndownu 6x8k 1x8k 6x8k 2x16k no ppi 5684
regulus 6x8k 1x8k 6x8k 2x16k no ppi 5645(a) 5638
reguluso 6x8k 1x8k 6x8k 2x16k no ppi 5645
regulusu 6x8k 1x8k 6x8k 2x16k no ppi 5955
mrviking 6x8k 1x8k 6x8k 2x16k no ppi 5876 5749
mrvikingj 6x8k 1x8k 6x8k 2x16k no ppi 5756
swat 6x8k 1x8k 6x8k 2x16k no ppi 5812 5805
flickys1 4x8k 1x8k 6x8k 2x16k no ppi ???? 5855
flickyo 4x8k 1x8k 6x8k 2x16k no ppi 5860(a)
flicky 2x16k 1x8k 6x8k 2x16k no pio 5979(a)
flickys2 2x16k 1x8k 6x8k 2x16k no pio 6622
wmatch 6x8k 1x8k 6x8k 2x16k no ppi ???? ????
bullfgt 6x8k 1x8k 6x8k 2x16k no ppi ???? 6069
thetogyu 3x16k 1x8k 6x8k 2x16k no pio 6073
spatter 3x16k 1x8k 6x8k 4x16k no pio 6394 6306
spattera 3x16k 1x8k 6x8k 4x16k no pio 6599 6306
ssanchan 3x16k 1x8k 6x8k 4x16k no pio 6312
pitfall2 3x16k 1x8k 6x8k 2x16k no pio 6458(a) 6454
pitfall2a 3x16k 1x8k 6x8k 2x16k no pio 6506
pitfall2u 3x16k 1x8k 6x8k 2x16k no pio 6625(a)
seganinj 3x16k 1x8k 6x8k 4x16k no pio ???? 6546
seganinju 3x16k 1x8k 6x8k 4x16k no pio 7150
nprinceso 3x16k 1x8k 6x8k 4x16k no pio 6552
nprincesb 3x16k 1x8k 6x8k 4x16k no pio bootleg
ninja 3x16k 1x8k 6x8k 4x16k no pio 6595
nprinces 6x8k 1x8k 6x8k 4x16k no ppi 6617
nprincesu 6x8k 1x8k 6x8k 4x16k no ppi 6578
imsorry 3x16k 1x8k 6x8k 2x16k no pio 6678 6645
imsorryj 3x16k 1x8k 6x8k 2x16k no pio 6649
teddybb 3x16k 1x8k 6x8k 4x16k no pio 6770 6735
teddybbo 3x16k 1x8k 6x8k 4x16k no pio 6741
teddybbobl 3x16k 1x8k 3x16k 4x16k no pio bootleg
hvymetal 3x32k 1x32k 6x16k 4x32k yes 6790 6778
myhero 3x16k 1x8k 6x8k 4x16k no pio 6964 6921
sscandal 3x16k 1x8k 6x8k 4x16k no pio 6927
myherok 3x16k 1x8k 6x8k 4x16k no pio bootleg?
4dwarrio 3x16k 1x8k 6x8k 4x16k no pio ???? ????
shtngmst 3x32k 1x32k 3x32k 7x32k yes 7102
choplift 3x32k 1x32k 3x32k 4x32k yes 7126 7120
chopliftu 3x32k 1x32k 3x32k 4x32k yes 7154
chopliftbl 3x32k 1x32k 3x32k 4x32k yes bootleg
raflesia 3x16k 1x8k 6x8k 4x16k no pio 7413 7408
raflesiau 6x8k 1x8k 6x8k 4x16k no ppi ???? ????
wboy2 6x8k 1x8k 6x8k 4x16k no ppi 7592 7485
wboy2u 6x8k 1x8k 6x8k 4x16k no ppi ????
wbdeluxe 6x8k 1x8k 6x8k 4x16k no ppi ????
wboy 3x16k 1x8k 6x8k 4x16k no pio 7491
wboyo 3x16k 1x8k 6x8k 4x16k no pio ????
wboy3 3x16k 1x8k 6x8k 4x16k no pio ????
wboyu 3x16k 1x8k 6x8k 4x16k no pio ????
wboy4 2x32k 1x32k 3x16k 2x32k no ????
wboysys2 2x32k 1x32k 3x32k 2x32k yes 7580
gardia 3x32k 1x16k 3x16k 4x32k yes 10255 10233
gardiab 3x32k 1x16k 3x16k 4x32k yes bootleg
brain 3x32k 1x32k 3x16k 3x32k yes ???? ????
tokisens 3x32k 1x32k 3x32k 4x32k yes 10963 10957
wbml 3x32k 1x32k 3x32k 4x32k yes 11033(a) 11027
wbmljo 3x32k 1x32k 3x32k 4x32k yes 11033
wbmljb 3x64k 1x32k 3x32k 4x32k yes bootleg
wbmlb 3x64k 1x32k 3x32k 4x32k yes bootleg
wbmlg 3x64k 1x32k 3x32k 4x32k yes bootleg
dakkochn 2x32k 1x32k 3x32k 4x32k yes 11225 11220
ufosensi 3x32k 1x32k 3x32k 4x32k yes 11663 11657
ufosensib 3x64k 1x32k 3x32k 4x32k yes bootleg
blockgal 2x16k 1x8k 6x8k 4x16k no ????
blockgalb 1x64k 1x8k 6x8k 4x16k no bootleg
nob 3x32k 1x16k 3x32k 4x32k yes
nobb 3x32k 1x16k 3x32k 4x32k yes
*******************************************************************************
Spatter (315-5099)
Sega 1984
This game runs on Sega System 1 hardware.
834-5583-12 SPATTER (sticker)
834-5542 daughter board with 4 eproms (EPR6306, EPR6307, EPR6308, EPR6309)
834-5540 daughter board with logic ICs
315-5099 custom Z80 CPU w/security
*******************************************************************************
Chop Lifter, Sega 1985
Hardware info by Guru
This game runs on Sega System 2 hardware.
171-5303-01
834-5795-03 CHOP LIFTER (sticker)
|-----------------------------------------------------------------|
|DSW2 DSW1 315-5011 EPR-7120.86 CXK5808 Z80A(2) 20MHz |
|TD62003 315-5012 EPR-7121.87 CXK5808 315-5152.10|
| EPR-7122.88 315-5138.11|
| EPR-7123.89 315-5049|
| |
| EPR-7152.90 |
|4 EPR-7153.91 M5M5165 |
|4 EPR-7154.92 M5M5165 |
|W M5M5165 |
|A 8255 DIP40 EPR-7127.4|
|Y 315-5139.50 EPR-7128.5|
| 2148 2148 2148 TL7705 EPR-7129.6|
| 2148 2148 2148 315-5025 |
| 315-5025 |
| 8MHz PR5317.37 315-5025 |
| Z80A(1) LED PR7117.8 |
| VOL 76489(1) PR7118.14 |
| 76489(2) EPR-7130.126 8147 PR7119.20 |
|LA4460 MB8128 8147 MB8128 |
|-----------------------------------------------------------------|
Notes:
315-5011 - Sega Custom IC (DIP40)
315-5012 - Sega Custom IC (DIP48)
315-5025 - Sega Custom IC (DIP18)
315-5138 - PAL16R4 (DIP20)
315-5139 - Signetics CK2605 (= PLS153) stamped '315-5139' (DIP20)
315-5049 - Sega Custom IC (SDIP64)
315-5152 - PAL16R4 (DIP20)
DIP40 - DIP40 socket for 8751 MCU. Some games like this version of Chop Lifter use a small
DIP40-sized board plugged into the socket marked 'SEGA 839-0001'. The board contains
nothing. The bottom of the board may have tracks going to other pins but it's obscured
by the socket connector. The top of the board has no tracks on it.
EPR-* - All EPROMs are 27C256 (DIP28)
MB8128 - Fujitsu MB8128 -10 2k x8 SRAM (DIP24)
2148 - Intel P2148H-3 1k x4 SRAM (DIP18)
2147 - Fujitsu MB2147-45 4k x1 SRAM (DIP18)
TL7705 - Texas Instruments TL7705 Voltage Supply Supervisor and Master Reset IC (DIP8)
LED - Power LED
8255 - NEC D8255 Programmable Peripheral Interface IC (DIP40)
Z80A(1) - Sharp LH0080A Z80A CPU, clock 4.000MHz [8/2]
Z80A(2) - Sharp LH0080A Z80A CPU, clock 4.000MHz [8/2]
CXK5808 - Sony CXK5808 1kBx8-bit SRAM (NDIP22)
M5M5165 - Mitsubishi M5M5165 8k x8 SRAM (DIP28)
SN76489(1) - Texas Instruments SN76489 4-channel Programmable Sound Generator. Clock 4.000MHz [8/2] (DIP16)
SN76489(2) - Texas Instruments SN76489 4-channel Programmable Sound Generator. Clock 2.000MHz [8/4] (DIP16)
LA4460 - Sanyo LA4460 12W AF Power Amplifier (SIL10)
TD62003 - Toshiba TD62003 7-channel Darlington Sink Driver (DIP16)
PR5317 - Fujitsu MB7114 Bipolar PROM (DIP16)
PR7117 - Fujitsu MB7114 Bipolar PROM (DIP16)
PR7118 - MMI 63S141 Bipolar PROM (DIP16)
PR7119 - Fujitsu MB7114 Bipolar PROM (DIP16)
Measurements
------------
OSC1 - 7.99992MHz
OSC2 - 19.99982MHz
VSync - 60.0952Hz
HSync - 15.4442kHz
***************************************************************************
Pitfall II The Lost Caverns, Sega, 1984
Hardware info by Guru
This game runs on Sega System 1 hardware. The version documented here is
the not-encrypted version.
The same PCB runs a few other games, including some official Sega conversions.
For example: My Hero, Teddy Boy Blues, Sega Ninja, Ninja Princess and several others.
The bootleg Pitfall II PCB is an exact 1:1 copy, including using the same encrypted ROMs,
and the custom chips have been replaced with plug-in daughterboards.
Sega Game ID#: 834-5627-10 PITFALL II (sticker). Also seen: -11, -12 and -13 stickers.
PCB#: 171-5054-02 (seen on some PCBs with (C) 1984). The (C) 1985 PCB does not have a 171 number on the PCB.
|--------------------------------------------------------------------------------|
| 20MHz 315-5063.IC67 |
| LED |
|Z80(1) EPR-6623.IC116 D4168 315-5062.IC41 |
| EPR-6624A.IC109 |
| EPR-6625.IC96 25LS251 2148 2148 2148 |
| |
| EPR-6454A.IC117 X X EPR-6455.IC05 2148 2148 2148 |
| |
| TLP521-4(x6) |--| |--| |
|4 |3 | |3 | 2148 |
|4 DIPSW_B |1 | |1 | 2148 2147 |
|W |5 | |5 | 2148 |
|A DIPSW_A || | || | 2148 EPR-6473A.IC61 |
|Y |5 | |5 | 315-5025 |
| |0 | |0 | EPR-6474A.IC62 74S201 |
| ULN2003 |1 | |1 | 8128 8128 315-5025 |
| |2 | |1 | EPR-6471A.IC63 |
| |--| |--| 315-5025 |
| Z80PIO Z80 8128 EPR-6472A.IC64 |
| 8MHz |
| VOL EPR-6462.IC120 EPR-6469A.IC65 |
| LA4460 76489A(1) 8128 |
| 76489A(2) PR5317.IC76 EPR-6470A.IC66 |
|--------------------------------------------------------------------------------|
Notes:
315-5011 - Sega custom DIP40 IC \
315-5012 - Sega custom DIP48 IC / The bootleg replaces these two chips with a plug-in daughterboard containing logic chips
Z80(1) - Z80 CPU. Clock input measures 3.76992MHz on first power on and changes to 3.65950MHz or 3.80062MHz during game play.
Replaced with encrypted Z80 with sticker '315-5093' on the encrypted version.
Some factory conversions have been seen with a plug-in daughterboard containing Z80, PAL and PROM and some later games
or later releases of the same game use a stock Z80 without encryption.
315-5025 - Sega custom IC. The bootleg replaces this with a plug-in daughterboard containing logic chips: 74LS299 (x6), 74LS273 (x3), 74LS157 (x3)
76489A(1) - Texas Instruments SN76489 4-channel Programmable Sound Generator. Clock 4.000MHz [8/2]
76489A(2) - Texas Instruments SN76489 4-channel Programmable Sound Generator. Clock 2.000MHz [8/4]
LA4460 - Sanyo LA4460 12W AF Power Amplifier
PR5317 - Fujitsu MB7114 Bipolar PROM (equivalent to 82S129)
Z80 - Zilog Z8400A Z80A CPU or Sharp LH0080A CPU or NEC D780C-1 CPU. Clock input 4.000MHz
Z80PIO - Zilog Z8420A Z80A-PIO or Sharp LH0081A Z80A-PIO. Clock input measures the same as the Z80(1) clock
D4168 - NEC D4168 8kBx8-bit SRAM, equivalent to 6264
8128 - Fujitsu MB8128 2kBx8-bit SRAM, equivalent to 6116
2148 - Fujitsu MB2148 1kBx4-bit SRAM
2147 - Fujitsu MB2147 4kBx1-bit SRAM
74S201 - Texas Instruments 256bx1-bit SRAM
315-5063 - National DMPAL16R4
315-5062 - National DMPAL16R4
25LS251 - AMD AM25LS251 8-Input Multiplexor
EPR-6623.IC116 \
EPR-6624A.IC109 / 27128 16kBx8-bit EPROM (main program, not-encrypted version)
EPR-6625.IC96 /
EPR-6462.IC120 - 2764 8kBx8-bit EPROM (sound program)
EPR-6473A.IC61 \
EPR-6474A.IC62 \
EPR-6471A.IC63 \
EPR-6472A.IC64 / 2764 8kBx8-bit EPROM (background tiles)
EPR-6469A.IC65 /
EPR-6470A.IC66 /
EPR-6454A.IC117 \
EPR-6455.IC05 / 27128 16kBx8-bit EPROM (sprites)
X - Empty socket
TLP521-4 - Toshiba TLP521-4 4-Channel Photocoupler
ULN2003 - Texas Instruments ULN2003 or Toshiba TD62003 7-channel Darlington Sink Driver
DIPSW_A,B - 8-position DIP switch
LED - Power LED
VSync - 60.0757Hz
HSync - 15.2585kHz
***************************************************************************
Flicky sets version notes:
flicky, flickyo
---------------
They both seem to be very similar programs. Difficulty is easier than the S1,S2 sets.
DIPs are also shared 100% with each other.
flickys1, flickys2
------------------
Very noticeably more difficult than the other two sets. DIPs have changes (less lives
and bonus options). There is no screen which shows the bonus lives values like the
other two sets, either. flickys1 allows for DEMO SOUND which none of the others sets
seem to have access to.
******************************************************************************/
#include "emu.h"
#include "system1.h"
#include "machine/segacrpt_device.h"
#include "cpu/z80/mc8123.h"
#include "speaker.h"
#define MASTER_CLOCK XTAL(20'000'000)
#define SOUND_CLOCK XTAL(8'000'000)
/*************************************
*
* Machine initialization
*
*************************************/
void system1_state::machine_start()
{
const u32 numbanks = (m_maincpu_region->bytes() - 0x10000) / 0x4000;
if (numbanks > 0)
m_bank1->configure_entries(0, numbanks, m_maincpu_region->base() + 0x10000, 0x4000);
else
m_bank1->configure_entry(0, m_maincpu_region->base() + 0x8000);
m_bank1->set_entry(0);
if (m_banked_decrypted_opcodes)
{
m_bank0d->set_base(m_banked_decrypted_opcodes.get());
m_bank1d->configure_entries(0, numbanks, m_banked_decrypted_opcodes.get() + 0x10000, 0x4000);
m_bank1d->set_entry(0);
}
save_item(NAME(m_dakkochn_mux_data));
save_item(NAME(m_adjust_cycles));
save_item(NAME(m_videomode_prev));
save_item(NAME(m_mcu_control));
save_item(NAME(m_nob_maincpu_latch));
save_item(NAME(m_nob_mcu_latch));
save_item(NAME(m_nob_mcu_status));
}
MACHINE_START_MEMBER(system1_state,system2)
{
system1_state::machine_start();
m_mute_xor = 0x01;
}
void system1_state::machine_reset()
{
m_dakkochn_mux_data = 0;
}
/*************************************
*
* Main CPU clocking
*
*************************************/
/*
A 20MHz crystal clocks an LS161 which counts up from either 10 or 11 to 16 before
carrying out and forcing a reload. The low bit of the reload value comes from the
Z80's /M1 signal. When /M1 is low (an opcode is being fetched), the reload count
is 10, which means the 20MHz clock is divided by 6. When /M1 is high, the reload
count is 11, which means the clock is divided by 5.
Since /M1 is low for 2 cycles during opcode fetch, this makes every opcode fetch
take an extra 2 20MHz clocks, which is 2/5th cycles at 4MHz.
*/
void system1_state::adjust_cycles(u8 data)
{
m_adjust_cycles = (m_adjust_cycles + 2) % 5;
if (m_adjust_cycles <= 1)
m_maincpu->adjust_icount(-1);
}
/*************************************
*
* ROM banking
*
*************************************/
void system1_state::bank44_custom_w(u8 data, u8 prevdata)
{
/* bank bits are bits 6 and 2 */
m_bank1->set_entry(((data & 0x40) >> 5) | ((data & 0x04) >> 2));
}
void system1_state::bank0c_custom_w(u8 data, u8 prevdata)
{
/* bank bits are bits 3 and 2 */
m_bank1->set_entry((data & 0x0c) >> 2);
if (m_bank1d)
m_bank1d->set_entry((data & 0x0c) >> 2);
}
void system1_state::videomode_w(u8 data)
{
/* bit 6 is connected to the 8751 IRQ */
if (m_mcu != nullptr)
m_mcu->set_input_line(MCS51_INT1_LINE, (data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
/* handle any custom banking or other stuff */
if (m_videomode_custom != nullptr)
(this->*m_videomode_custom)(data, m_videomode_prev);
m_videomode_prev = data;
/* bit 0 is for the coin counters */
machine().bookkeeping().coin_counter_w(0, data & 1);
/* remaining signals are video-related */
common_videomode_w(data);
}
/*************************************
*
* DakkoChan House custom inputs
*
*************************************/
CUSTOM_INPUT_MEMBER(system1_state::dakkochn_mux_data_r)
{
static const char *const ports[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4", "KEY5", "KEY6" };
return ioport(ports[m_dakkochn_mux_data])->read();
}
CUSTOM_INPUT_MEMBER(system1_state::dakkochn_mux_status_r)
{
/* reads from here indicate which mux port is selected */
return 1 << (m_dakkochn_mux_data);
}
void system1_state::dakkochn_custom_w(u8 data, u8 prevdata)
{
/* bit 1 toggling on clocks the mux; we store the previous state in the high bit of dakkochn_mux_data */
if ((data & 0x02) && !(prevdata & 0x02))
m_dakkochn_mux_data = (m_dakkochn_mux_data + 1) % 7;
/* remaining stuff acts like bank0c */
bank0c_custom_w(data, prevdata);
}
/*************************************
*
* Shooting Master gun input
*
*************************************/
u8 system1_state::shtngmst_gunx_r()
{
// x is slightly offset, and has a range of 00-fe
u8 x = ioport("GUNX")->read() - 0x12;
return (x == 0xff) ? 0xfe : x;
}
/*************************************
*
* Sound I/O
*
*************************************/
void system1_state::sound_control_w(u8 data)
{
/* bit 0 = MUTE (inverted sense on System 2) */
machine().sound().system_mute((data ^ m_mute_xor) & 1);
/* bit 6 = feedback from sound board that read occurred */
/* bit 7 controls the sound CPU's NMI line */
m_soundcpu->set_input_line(INPUT_LINE_NMI, (data & 0x80) ? CLEAR_LINE : ASSERT_LINE);
/* remaining bits are used for video RAM banking */
videoram_bank_w(data);
}
u8 system1_state::sound_data_r()
{
/* if we have an 8255 PPI, get the data from the port and toggle the ack */
if (m_ppi8255 != nullptr)
{
m_ppi8255->pc6_w(0);
m_ppi8255->pc6_w(1);
return m_soundlatch->read();
}
/* if we have a Z80 PIO, get the data from the port and toggle the strobe */
else if (m_pio != nullptr)
{
u8 data = m_pio->port_read(z80pio_device::PORT_A);
m_pio->strobe(z80pio_device::PORT_A, false);
m_pio->strobe(z80pio_device::PORT_A, true);
return data;
}
return 0xff;
}
void system1_state::soundport_w(u8 data)
{
/* boost interleave when communicating with the sound CPU */
m_soundlatch->write(data);
machine().scheduler().perfect_quantum(attotime::from_usec(100));
}
TIMER_DEVICE_CALLBACK_MEMBER(system1_state::soundirq_gen)
{
/* sound IRQ is generated on 32V, 96V, ... and auto-acknowledged */
m_soundcpu->set_input_line(0, HOLD_LINE);
}
/*************************************
*
* MCU I/O
*
*************************************/
void system1_state::mcu_control_w(u8 data)
{
/*
Bit 7 -> connects to TD62003 pins 5 & 6 @ IC151
Bit 6 -> via PLS153, when high, asserts the BUSREQ signal, halting the Z80
Bit 5 -> n/c
Bit 4 -> (with bit 3) Memory select: 0=Z80 program space, 1=banked ROM, 2=Z80 I/O space, 3=watchdog?
Bit 3 ->
Bit 2 -> n/c
Bit 1 -> n/c
Bit 0 -> Directly connected to Z80 /INT line
*/
/* boost interleave to ensure that the MCU can break the Z80 out of a HALT */
if (!BIT(m_mcu_control, 6) && BIT(data, 6))
machine().scheduler().perfect_quantum(attotime::from_usec(10));
m_mcu_control = data;
m_maincpu->set_input_line(INPUT_LINE_HALT, (data & 0x40) ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(0, (data & 0x01) ? CLEAR_LINE : ASSERT_LINE);
}
void system1_state::mcu_io_w(offs_t offset, u8 data)
{
switch ((m_mcu_control >> 3) & 3)
{
case 0:
m_maincpu->space(AS_PROGRAM).write_byte(offset, data);
break;
case 2:
m_maincpu->space(AS_IO).write_byte(offset, data);
break;
default:
logerror("%03X: MCU movx write mode %02X offset %04X = %02X\n",
m_mcu->pc(), m_mcu_control, offset, data);
break;
}
}
u8 system1_state::mcu_io_r(offs_t offset)
{
switch ((m_mcu_control >> 3) & 3)
{
case 0:
return m_maincpu->space(AS_PROGRAM).read_byte(offset);
case 1:
return m_maincpu_region->base()[offset + 0x10000];
case 2:
return m_maincpu->space(AS_IO).read_byte(offset);
default:
logerror("%03X: MCU movx read mode %02X offset %04X\n",
m_mcu->pc(), m_mcu_control, offset);
return 0xff;
}
}
TIMER_DEVICE_CALLBACK_MEMBER(system1_state::mcu_t0_callback)
{
/* The T0 line is clocked by something; if it is not clocked fast
enough, the MCU will fail; on shtngmst this happens after 3
VBLANKs without a tick.
choplift is even more picky about it, affecting scroll speed
*/
m_mcu->set_input_line(MCS51_T0_LINE, ASSERT_LINE);
m_mcu->set_input_line(MCS51_T0_LINE, CLEAR_LINE);
}
/*************************************
*
* nob MCU
*
*************************************/
u8 system1_state::nob_mcu_latch_r()
{
return m_nob_mcu_latch;
}
void system1_state::nob_mcu_latch_w(u8 data)
{
m_nob_mcu_latch = data;
}
void system1_state::nob_mcu_status_w(u8 data)
{
m_nob_mcu_status = data;
}
void system1_state::nob_mcu_control_p2_w(u8 data)
{
/* bit 0 triggers a read from MCU port 0 */
if (((m_mcu_control ^ data) & 0x01) && !(data & 0x01))
m_nob_mcu_latch = m_nob_maincpu_latch;
/* bit 1 triggers a write from MCU port 0 */
if (((m_mcu_control ^ data) & 0x02) && !(data & 0x02))
m_nob_maincpu_latch = m_nob_mcu_latch;
/* bit 2 is toggled once near the end of an IRQ */
if (((m_mcu_control ^ data) & 0x04) && !(data & 0x04))
m_mcu->set_input_line(MCS51_INT0_LINE, CLEAR_LINE);
/* bit 3 is toggled once at the start of an IRQ, and again at the end */
if (((m_mcu_control ^ data) & 0x08) && !(data & 0x08))
{
//logerror("MCU IRQ(8) toggle\n");
}
m_mcu_control = data;
}
u8 system1_state::nob_maincpu_latch_r()
{
return m_nob_maincpu_latch;
}
void system1_state::nob_maincpu_latch_w(u8 data)
{
m_nob_maincpu_latch = data;
m_mcu->set_input_line(MCS51_INT0_LINE, ASSERT_LINE);
machine().scheduler().perfect_quantum(attotime::from_usec(100));
}
u8 system1_state::nob_mcu_status_r()
{
return m_nob_mcu_status;
}
/*************************************
*
* nob bootleg protection
*
*************************************/
u8 system1_state::nobb_inport1c_r()
{
// logerror("IN $1c : pc = %04x - data = 0x80\n",m_maincpu->pc());
return(0x80); // infinite loop (at 0x0fb3) until bit 7 is set
}
u8 system1_state::nobb_inport22_r()
{
// logerror("IN $22 : pc = %04x - data = %02x\n",m_maincpu->pc(),nobb_inport17_step);
return(0);//nobb_inport17_step);
}
u8 system1_state::nobb_inport23_r()
{
// logerror("IN $23 : pc = %04x - step = %02x\n",m_maincpu->pc(),m_nobb_inport23_step);
return(m_nobb_inport23_step);
}
void system1_state::nobb_outport24_w(u8 data)
{
// logerror("OUT $24 : pc = %04x - data = %02x\n",m_maincpu->pc(),data);
m_nobb_inport23_step = data;
}
/*************************************
*
* Main CPU address maps
*
*************************************/
/* main memory map */
void system1_state::system1_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0xbfff).bankr("bank1");
map(0xc000, 0xcfff).ram().share("ram");
map(0xd000, 0xd7ff).ram().share("spriteram");
map(0xd800, 0xdfff).ram().w(FUNC(system1_state::paletteram_w)).share("paletteram");
map(0xe000, 0xefff).rw(FUNC(system1_state::videoram_r), FUNC(system1_state::videoram_w));
map(0xf000, 0xf3ff).rw(FUNC(system1_state::mixer_collision_r), FUNC(system1_state::mixer_collision_w));
map(0xf400, 0xf7ff).w(FUNC(system1_state::mixer_collision_reset_w));
map(0xf800, 0xfbff).rw(FUNC(system1_state::sprite_collision_r), FUNC(system1_state::sprite_collision_w));
map(0xfc00, 0xffff).w(FUNC(system1_state::sprite_collision_reset_w));
}
void system1_state::decrypted_opcodes_map(address_map &map)
{
map(0x0000, 0x7fff).rom().share("decrypted_opcodes");
map(0x8000, 0xbfff).bankr("bank1");
map(0xc000, 0xcfff).ram().share("ram");
map(0xd000, 0xd7ff).ram().share("spriteram");
map(0xd800, 0xdfff).ram().w(FUNC(system1_state::paletteram_w)).share("paletteram");
}
void system1_state::banked_decrypted_opcodes_map(address_map &map)
{
map(0x0000, 0x7fff).bankr("bank0d");
map(0x8000, 0xbfff).bankr("bank1d");
map(0xc000, 0xcfff).ram().share("ram");
map(0xd000, 0xd7ff).ram().share("spriteram");
map(0xd800, 0xdfff).ram().w(FUNC(system1_state::paletteram_w)).share("paletteram");
}
/* same as normal System 1 except address map is shuffled (RAM/collision are swapped) */
void system1_state::nobo_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0xbfff).bankr("bank1");
map(0xc000, 0xc3ff).rw(FUNC(system1_state::mixer_collision_r), FUNC(system1_state::mixer_collision_w));
map(0xc400, 0xc7ff).w(FUNC(system1_state::mixer_collision_reset_w));
map(0xc800, 0xcbff).rw(FUNC(system1_state::sprite_collision_r), FUNC(system1_state::sprite_collision_w));
map(0xcc00, 0xcfff).w(FUNC(system1_state::sprite_collision_reset_w));
map(0xd000, 0xd7ff).ram().share("spriteram");
map(0xd800, 0xdfff).ram().w(FUNC(system1_state::paletteram_w)).share("paletteram");
map(0xe000, 0xefff).rw(FUNC(system1_state::videoram_r), FUNC(system1_state::videoram_w));
map(0xf000, 0xffff).ram().share("ram");
}
/* I/O map for systems with an 8255 PPI */
void system1_state::system1_ppi_io_map(address_map &map)
{
map.global_mask(0x1f);
map(0x00, 0x00).mirror(0x03).portr("P1");
map(0x04, 0x04).mirror(0x03).portr("P2");
map(0x08, 0x08).mirror(0x03).portr("SYSTEM");
map(0x0c, 0x0c).mirror(0x02).portr("SWA"); /* DIP2 */
map(0x0d, 0x0d).mirror(0x02).portr("SWB"); /* DIP1 some games read it from here... */
map(0x10, 0x10).mirror(0x03).portr("SWB"); /* DIP1 ... and some others from here but there are games which check BOTH! */
map(0x14, 0x17).rw(m_ppi8255, FUNC(i8255_device::read), FUNC(i8255_device::write));
}
/* I/O map for systems with a Z80 PIO chip */
void system1_state::system1_pio_io_map(address_map &map)
{
map.global_mask(0x1f);
map(0x00, 0x00).mirror(0x03).portr("P1");
map(0x04, 0x04).mirror(0x03).portr("P2");
map(0x08, 0x08).mirror(0x03).portr("SYSTEM");
map(0x0c, 0x0c).mirror(0x02).portr("SWA"); /* DIP2 */
map(0x0d, 0x0d).mirror(0x02).portr("SWB"); /* DIP1 some games read it from here... */
map(0x10, 0x10).mirror(0x03).portr("SWB"); /* DIP1 ... and some others from here but there are games which check BOTH! */
map(0x18, 0x1b).rw("pio", FUNC(z80pio_device::read), FUNC(z80pio_device::write));
}
void system1_state::blockgal_pio_io_map(address_map &map)
{
map.global_mask(0x1f);
map(0x00, 0x00).mirror(0x03).portr("P1");
map(0x04, 0x04).mirror(0x03).portr("P2");
map(0x08, 0x08).mirror(0x03).portr("SYSTEM");
map(0x0d, 0x0d).mirror(0x02).portr("SWA"); // DIP2
map(0x10, 0x10).mirror(0x03).portr("SWB"); // DIP1
map(0x18, 0x1b).rw("pio", FUNC(z80pio_device::read), FUNC(z80pio_device::write));
}
/*************************************
*
* Sound CPU address maps
*
*************************************/
void system1_state::sound_map(address_map &map)
{
map(0x0000, 0x7fff).rom();
map(0x8000, 0x87ff).mirror(0x1800).ram();
map(0xa000, 0xa000).mirror(0x1fff).w("sn1", FUNC(sn76489a_device::write));
map(0xc000, 0xc000).mirror(0x1fff).w("sn2", FUNC(sn76489a_device::write));
map(0xe000, 0xe000).mirror(0x1fff).r(FUNC(system1_state::sound_data_r));
}
/*************************************
*
* MCU address maps
*
*************************************/
void system1_state::mcu_io_map(address_map &map)
{
map(0x0000, 0xffff).rw(FUNC(system1_state::mcu_io_r), FUNC(system1_state::mcu_io_w));
}
/*************************************
*
* Generic port definitions
*
*************************************/
static INPUT_PORTS_START( system1_generic )
PORT_START("P1")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
PORT_START("P2")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
PORT_START("SYSTEM")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_SERVICE_NO_TOGGLE( 0x04, IP_ACTIVE_LOW )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("SWA")
PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SWA:1,2,3,4")
PORT_DIPSETTING( 0x07, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x08, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x09, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x05, "2 Coins/1 Credit 5/3 6/4" )
PORT_DIPSETTING( 0x04, "2 Coins/1 Credit 4/3" )
PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x01, "1 Coin/1 Credit 2/3" )
PORT_DIPSETTING( 0x02, "1 Coin/1 Credit 4/5" )
PORT_DIPSETTING( 0x03, "1 Coin/1 Credit 5/6" )
PORT_DIPSETTING( 0x06, DEF_STR( 2C_3C ) )
PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) )
PORT_DIPSETTING( 0x0a, DEF_STR( 1C_6C ) )
/* PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) Not allowed by mame coinage sorting, but valid */
PORT_DIPNAME( 0xf0, 0xf0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SWA:5,6,7,8")
PORT_DIPSETTING( 0x70, DEF_STR( 4C_1C ) )
PORT_DIPSETTING( 0x80, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x90, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x50, "2 Coins/1 Credit 5/3 6/4" )
PORT_DIPSETTING( 0x40, "2 Coins/1 Credit 4/3" )
PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x10, "1 Coin/1 Credit 2/3" )
PORT_DIPSETTING( 0x20, "1 Coin/1 Credit 4/5" )
PORT_DIPSETTING( 0x30, "1 Coin/1 Credit 5/6" )
PORT_DIPSETTING( 0x60, DEF_STR( 2C_3C ) )
PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) )
PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) )
/* PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) Not allowed by mame coinage sorting, but valid */
PORT_START("SWB")
PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SWB:1")
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SWB:2" )
PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SWB:3" )
PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SWB:4" )
PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SWB:5" )
PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SWB:6" )
PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SWB:7" )
/* If you don't like the description, feel free to change it */
PORT_DIPNAME( 0x80, 0x80, "SW 0 Read From" ) PORT_DIPLOCATION("SWB:8")
PORT_DIPSETTING( 0x80, "Port $0D" )
PORT_DIPSETTING( 0x00, "Port $10" )
INPUT_PORTS_END
/*************************************
*
* Game-specific port definitions
*
*************************************/
static INPUT_PORTS_START( starjack )
PORT_INCLUDE( system1_generic )
PORT_MODIFY("SWB")
PORT_DIPNAME( 0x06, 0x06, DEF_STR( Lives ) ) PORT_DIPLOCATION("SWB:2,3")
PORT_DIPSETTING( 0x06, "3" )
PORT_DIPSETTING( 0x04, "4" )
PORT_DIPSETTING( 0x02, "5" )
PORT_DIPSETTING( 0x00, DEF_STR( Infinite ) )
PORT_DIPNAME( 0x38, 0x30, DEF_STR (Bonus_Life ) ) PORT_DIPLOCATION("SWB:4,5,6")
PORT_DIPSETTING( 0x38, "Every 20k" )
PORT_DIPSETTING( 0x28, "Every 30k" )
PORT_DIPSETTING( 0x18, "Every 40k" )
PORT_DIPSETTING( 0x08, "Every 50k" )
PORT_DIPSETTING( 0x30, "20k, then every 30k" )
PORT_DIPSETTING( 0x20, "30k, then every 40k" )
PORT_DIPSETTING( 0x10, "40k, then every 50k" )
PORT_DIPSETTING( 0x00, "50k, then every 60k" )
PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWB:7,8")
PORT_DIPSETTING( 0xc0, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x80, DEF_STR( Medium ) )
PORT_DIPSETTING( 0x40, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
INPUT_PORTS_END
static INPUT_PORTS_START( starjacks )
PORT_INCLUDE( starjack )
PORT_MODIFY("SWB")
PORT_DIPNAME( 0x08, 0x08, "Ship" ) PORT_DIPLOCATION("SWB:4")
PORT_DIPSETTING( 0x08, DEF_STR( Single ) )
PORT_DIPSETTING( 0x00, "Multi" )
PORT_DIPNAME( 0x30, 0x30, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SWB:5,6")
PORT_DIPSETTING( 0x30, "30k, then every 40k" )
PORT_DIPSETTING( 0x20, "40k, then every 50k" )
PORT_DIPSETTING( 0x10, "50k, then every 60k" )
PORT_DIPSETTING( 0x00, "60k, then every 70k" )
INPUT_PORTS_END
static INPUT_PORTS_START( regulus )
PORT_INCLUDE( system1_generic )
PORT_MODIFY("SWB")
PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Lives ) ) PORT_DIPLOCATION("SWB:3,4")
PORT_DIPSETTING( 0x0c, "3" )
PORT_DIPSETTING( 0x08, "4" )
PORT_DIPSETTING( 0x04, "5" )
PORT_DIPSETTING( 0x00, DEF_STR( Infinite ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWB:7")
PORT_DIPSETTING( 0x40, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hard ) )
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Allow_Continue ) ) PORT_DIPLOCATION("SWB:8")
PORT_DIPSETTING( 0x80, DEF_STR( No ) )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
INPUT_PORTS_END
/* Same as 'regulus', but no DEF_STR( Allow_Continue ) Dip Switch */
static INPUT_PORTS_START( reguluso )
PORT_INCLUDE( regulus )
PORT_MODIFY("SWB")
PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SWB:8" )
INPUT_PORTS_END
static INPUT_PORTS_START( upndown )
PORT_INCLUDE( system1_generic )
PORT_MODIFY("P1")
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* no button 2 */
PORT_MODIFY("P2")