cpu/f2mc16: Add and fix several instructions

[qufb]

Added instructions required to emulate Tomy Prin-C. Also added some fatal errors in order to not silently ignore missing instructions.

The following bugs were fixed:

• ADD A, #imm8/SUB A, #imm8: bits 8 to 15 of A must be zero-extended;
• ADDL A, @RWx + disp8/SUBL A, @RWx + disp8/CMPL A, @RWx + disp8/ANDL A, @RWx + disp8: 8-bit displacement fetched as 4 instead of 1 byte;
• ADDSP #imm8: 8-bit immediate must be sign-extended;
• BLE/BGT/BHI: Operator or must have precedence over checked condition value;
• EXT: Z flag was set on PC instead of PS;
• MOVW @RWx + disp8, #imm16: 8-bit displacement fetched as 2 instead of 1 byte;
• MOV A, @RWx + RW7/MOV @RWx + RW7, A: PC incremented by 3 instead of 2 bytes;
• MOV @RWx + RW7, #imm8: Operand fetched with 3-bit instead of 1-bit mask, also missing fetch to 8-bit immediate (reused previous variable value);
• MOVSI ADB, DTB/FILSI ADB: Only first loop iteration was computed, and PC was only conditionally set (also took the chance to generalize these instructions for all banks);
• MOVW @RWx + disp16, #imm16/ADD @RWx, A/ORW A, @RWx: Operand fetched with 7-bit instead of 3-bit mask;
• MOVX A, @RWx + disp8: missing NZ flags update;

Adjusted instructions with incorrect number of cycles:

• ASRW A, R0/LSRW A, R0/LSR A, R0: used 5 instead of 1 additional cycles per iteration;
• LSLL A, R0: 6 cycles were discounted again when R0 != 0;
• Several instructions were not considering additional addressing cycles;