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Better handling of instructions on 64bit variables #231

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mkst opened this issue May 3, 2022 · 1 comment
Open

Better handling of instructions on 64bit variables #231

mkst opened this issue May 3, 2022 · 1 comment

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@mkst
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mkst commented May 3, 2022

Example scratch: https://decomp.me/scratch/z6j5r

    x = (sp68.unk0 << 8) - arg0->xVelocity.w;
    z = (sp68.unk2 << 8) - arg0->zVelocity.w;
    y = (sp68.unk4 << 8) - arg0->yVelocity.w;

    temp_f4 = sqrtf((s64)x*x + (s64)z*z + (s64)y*y);

The sqrtf call results in calls to __ll_mul for the s64 multiplication as well as __ll_to_f for the s64 -> f32 conversion.

m2c writes out these functions verbatim (with all the weird things the compiler does behind the scenes):

    sp58 = (sp68 << 8) - arg0->unk1C;
    temp_v0 = (sp6A << 8) - arg0->unk20;
    temp_a2 = temp_v0 >> 0x1F;
    sp60 = (sp6C << 8) - arg0->unk24;
    sp28 = temp_a2;
    sp2C = temp_v0;
    sp5C = temp_v0;
    temp_ret = __ll_mul(temp_a2, temp_v0, temp_a2, temp_v0);
    temp_v1 = (u32) (u64) temp_ret;
    sp38 = temp_ret;
    sp3C = temp_v1;
    temp_a2_2 = sp58 >> 0x1F;
    sp28 = temp_a2_2;
    sp2C = sp58;
    temp_ret_2 = __ll_mul(temp_a2_2, sp58, temp_a2_2, sp58);
    temp_v1_2 = (u32) (u64) temp_ret_2;
    sp40 = temp_ret_2;
    sp44 = temp_v1_2;
    temp_a2_3 = sp60 >> 0x1F;
    sp28 = temp_a2_3;
    sp2C = sp60;
    temp_ret_3 = __ll_mul(temp_a2_3, sp60, temp_a2_3, sp60);
    temp_t5 = (u32) (u64) temp_ret_3 + sp44;
    temp_a1 = temp_t5 + sp3C;
    temp_f4 = (s32) sqrtf(__ll_to_f((temp_a1 < sp3C) + ((temp_t5 < sp44) + temp_ret_3 + sp40) + sp38, temp_a1));

It would be wonderful if these kind of patterns could be better detected and replaced by the s64 casts.

PS - is this an IDO specific quirk or does GCC compilation do this too?

@zbanks
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zbanks commented May 4, 2022

I put together a quick test to see how useful it would be to try to handle the __ll_* functions as normal arithmetic instructions: dword-arith.

Looking at SSSV's matrix functions, the output and diff do look better, but they do highlight the fact that m2c is merely ignoring the upper register in the 64-bit value.

The output will probably be pretty close, as long as that upper register is always either 0 or a sign bit -- but, if there's anything else there, m2c would ignore it entirely. (This makes me hesitant to try to incorporate this into the main branch.)

As mentioned on Discord, m2c will need a bit more work to support for 64-bit values, even on MIPS.

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