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Index range of array aggregate with others choice #641

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@amb5l

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@amb5l

I am assigning an unconstrained std_logic_vector signal in a procedure: q <= (others => '0');

NVC does not like this:
Error: index range of array aggregate with others choice cannot be determined from the context

Xilinx XSim is happy with this code, and I think GHDL is too (although it fails for other reasons).

Here's an MCVE, which you can try with nvc --std=2008 -a --relaxed mcve.vhd:

library ieee;
  use ieee.std_logic_1164.all;

entity mcve is
  port(
    clk : in  std_logic;
    rst : in  std_logic;
    d   : in  std_logic_vector(31 downto 0);
    q   : out std_logic_vector(31 downto 0)
  );
end entity mcve;

architecture arch of mcve is

  procedure reg_bus(
    signal clk : in  std_logic;
    signal rst : in  std_logic;
    signal d   : in  std_logic_vector;
    signal q   : out std_logic_vector
  ) is
  begin
    if rising_edge(clk) then
      if rst = '1' then
        q <= (others => '0');
      else
        q <= d;
      end if;
    end if;
  end procedure reg_bus;

begin

  reg_bus(clk,rst,d,q);

end architecture arch;

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