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README.html
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<div class="document" id="color-maker-user-manual">
<h1 class="title">color_maker user manual</h1>
<table border="1" class="docutils">
<colgroup>
<col width="25%" />
<col width="75%" />
</colgroup>
<tbody valign="top">
<tr><td><strong>Title</strong></td>
<td>color_maker-s3esk (simple VGA tester)</td>
</tr>
<tr><td><strong>Author</strong></td>
<td>Nikolaos Kavvadias (C) 2014, 2015, 2016</td>
</tr>
<tr><td><strong>Contact</strong></td>
<td><a class="reference external" href="mailto:nikos@nkavvadias.com">nikos@nkavvadias.com</a></td>
</tr>
<tr><td><strong>Source</strong></td>
<td>Mike Field (for the VGA controller; see AUTHORS)</td>
</tr>
<tr><td><strong>Website</strong></td>
<td><a class="reference external" href="http://www.nkavvadias.com">http://www.nkavvadias.com</a></td>
</tr>
<tr><td><strong>Release Date</strong></td>
<td>08 August 2016</td>
</tr>
<tr><td><strong>Version</strong></td>
<td>1.1.1</td>
</tr>
<tr><td><strong>Rev. history</strong></td>
<td> </td>
</tr>
<tr><td><strong>v1.1.1</strong></td>
<td><p class="first">2016-08-08</p>
<p class="last">Added clean-up script.</p>
</td>
</tr>
<tr><td><strong>v1.1.0</strong></td>
<td><p class="first">2016-07-10</p>
<p class="last">GHDL simulation scripts and generation of log file for
VGA simulation.</p>
</td>
</tr>
<tr><td><strong>v1.0.2</strong></td>
<td><p class="first">2016-07-10</p>
<p class="last">Update for 2016.</p>
</td>
</tr>
<tr><td><strong>v1.0.1</strong></td>
<td><p class="first">2014-06-18</p>
<p class="last">Changed README to README.rst; COPYING to LICENSE.</p>
</td>
</tr>
<tr><td><strong>v1.0.0</strong></td>
<td><p class="first">2014-06-09</p>
<p class="last">Initial release for the Spartan-3E Starter kit board.</p>
</td>
</tr>
</tbody>
</table>
<div class="section" id="introduction">
<h1>1. Introduction</h1>
<p><tt class="docutils literal">color_maker</tt> is a simple design for testing VGA output. This version of the
<tt class="docutils literal">color_maker</tt> produces 3-bit RGB color (R1G1B1) as supported by the Xilinx
Spartan-3E starter kit board. 3 out of the 4 available slide switches
(specifically switches SW2, SW1, SW0) are used for setting a specific color
out of the eight unique colors that are available.</p>
<p>The following table summarizes the available colors.</p>
<blockquote>
<table border="1" class="docutils">
<colgroup>
<col width="7%" />
<col width="7%" />
<col width="7%" />
<col width="80%" />
</colgroup>
<thead valign="bottom">
<tr><th class="head">R</th>
<th class="head">G</th>
<th class="head">B</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr><td>0</td>
<td>0</td>
<td>0</td>
<td>Black (Noir)</td>
</tr>
<tr><td>0</td>
<td>0</td>
<td>1</td>
<td>Blue</td>
</tr>
<tr><td>0</td>
<td>1</td>
<td>0</td>
<td>Green</td>
</tr>
<tr><td>0</td>
<td>1</td>
<td>1</td>
<td>Cyan</td>
</tr>
<tr><td>1</td>
<td>0</td>
<td>0</td>
<td>Red</td>
</tr>
<tr><td>1</td>
<td>0</td>
<td>1</td>
<td>Magenta</td>
</tr>
<tr><td>1</td>
<td>1</td>
<td>0</td>
<td>Yellow</td>
</tr>
<tr><td>1</td>
<td>1</td>
<td>1</td>
<td>White</td>
</tr>
</tbody>
</table>
</blockquote>
<p>For the standard VGA resolution (<a class="reference external" href="mailto:640x480@60Hz">640x480@60Hz</a>), a 25MHz clock is used, as
produced by the <tt class="docutils literal">clockdiv</tt> clock divider (divide by 2). The VGA controller
is implemented by <tt class="docutils literal">vgactrl.vhd</tt>. The color selection logic is very
simple and directly assigns SW2 to the R, SW1 to G and SW0 to the B component.
For <a class="reference external" href="mailto:800x600@72Hz">800x600@72Hz</a>, a 50 MHz clock should be used.</p>
<p>The <tt class="docutils literal">vga_controller</tt> design has been adapted from the work by Mike Field:
<a class="reference external" href="http://hamsterworks.co.nz/mediawiki/index.php/Hidef_snow">http://hamsterworks.co.nz/mediawiki/index.php/Hidef_snow</a></p>
</div>
<div class="section" id="file-listing">
<h1>2. File listing</h1>
<p>The <tt class="docutils literal">color_maker</tt> distribution includes the following files:</p>
<table border="1" class="docutils">
<colgroup>
<col width="30%" />
<col width="70%" />
</colgroup>
<tbody valign="top">
<tr><td>/color_maker-s3esk</td>
<td>Top-level directory</td>
</tr>
<tr><td>AUTHORS</td>
<td>List of authors.</td>
</tr>
<tr><td>LICENSE</td>
<td>3-clause modified BSD license.</td>
</tr>
<tr><td>README.rst</td>
<td>This file.</td>
</tr>
<tr><td>README.html</td>
<td>HTML version of README.rst.</td>
</tr>
<tr><td>README.pdf</td>
<td>PDF version of README.rst.</td>
</tr>
<tr><td>clean.sh</td>
<td>A bash script for cleaning simulation artifacts.</td>
</tr>
<tr><td>clockdiv.vhd</td>
<td>Configurable, portable, clock divider.</td>
</tr>
<tr><td>color_maker.vhd</td>
<td>Color assignment logic.</td>
</tr>
<tr><td>color_maker_top.ucf</td>
<td>User Constraints File for the XC3S500E-FG320-4
device.</td>
</tr>
<tr><td>color_maker_top.vhd</td>
<td>The top-level RTL VHDL design file.</td>
</tr>
<tr><td>color_maker_top_tb.vhd</td>
<td>Testbench for the top-level RTL VHDL design file.</td>
</tr>
<tr><td>color_maker_top-syn.sh</td>
<td>Bash shell script for synthesizing the
<tt class="docutils literal">color_maker</tt> design with Xilinx ISE.</td>
</tr>
<tr><td>ghdl.mk</td>
<td>Makefile for VHDL simulation with GHDL.</td>
</tr>
<tr><td>ghdl.sh</td>
<td>Bash shell script for running the simulation with
GHDL.</td>
</tr>
<tr><td>impact_s3esk.bat</td>
<td>Windows Batch file for automatically invoking Xilinx
IMPACT in order to download the generated bitstream
to the target hardware.</td>
</tr>
<tr><td>rst2docs.sh</td>
<td>Bash script for generating the HTML and PDF versions.</td>
</tr>
<tr><td>vgactrl.vhd</td>
<td>RTL VHDL code for the VGA controller.</td>
</tr>
<tr><td>xst.mk</td>
<td>Standard Makefile for command-line usage of ISE.</td>
</tr>
</tbody>
</table>
</div>
<div class="section" id="usage">
<h1>3. Usage</h1>
<p>The <tt class="docutils literal">color_maker</tt> distribution includes scripts for logic synthesis automation
supporting Xilinx ISE. The corresponding synthesis script can be edited in order
to specify the following for adapting to the user's setup:</p>
<ul class="simple">
<li><tt class="docutils literal">XDIR</tt>: the path to the <tt class="docutils literal">/bin</tt> subdirectory of the Xilinx ISE/XST
installation where the <tt class="docutils literal">xst.exe</tt> executable is placed</li>
<li><tt class="docutils literal">arch</tt>: specific FPGA architecture (device family) to be used for synthesis</li>
<li><tt class="docutils literal">part</tt>: specific FPGA part (device) to be used for synthesis</li>
</ul>
<div class="section" id="running-the-simulation-script">
<h2>3.1. Running the simulation script</h2>
<p>This step assumes that the GHDL executable is in the user's <tt class="docutils literal">$PATH</tt>, e.g., by
using:</p>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ export <span class="pre">PATH=/path/to/ghld/bin:$PATH</span></tt></div>
</div>
<p>Then the simulation shell script can be run from a UNIX/Linux/Cygwin command line:</p>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ ./ghdl.sh</tt></div>
</div>
<p>This will produce a text file named <tt class="docutils literal">color_maker_top_results.txt</tt> with the values
of current time whenever a clock event occurs (as integer) and the signals <tt class="docutils literal">hs</tt>,
<tt class="docutils literal">vs</tt>, <tt class="docutils literal">red</tt>, <tt class="docutils literal">green</tt> and <tt class="docutils literal">blue</tt> (as binary). This can be used by an external
tool, the VGA simulator (<a class="reference external" href="http://ericeastwood.com/lab/vga-simulator/">http://ericeastwood.com/lab/vga-simulator/</a>) for visualizing
the outcome if a VGA/CRT monitor would be driven. A downloadable version of the
VGA simulator also exists: <a class="reference external" href="https://github.com/MadLittleMods/vga-simulator">https://github.com/MadLittleMods/vga-simulator</a></p>
<p>In order to work with the VGA simulator without further changes, the red, green and
blue signals are extended to 3, 3, and 2 bits, respectively in the testbench.</p>
<p>To clean up simulation artifacts, including the generated diagnostics file, use
the <tt class="docutils literal">clean.sh</tt> script:</p>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ ./clean.sh</tt></div>
</div>
</div>
<div class="section" id="running-the-synthesis-script">
<h2>3.2. Running the synthesis script</h2>
<p>For running the Xilinx ISE synthesis tool, generating FPGA configuration
bistream and downloading to the target device, execute the corresponding script
from within the <tt class="docutils literal"><span class="pre">color_maker-s3esk</span></tt> directory:</p>
<div class="line-block">
<div class="line"><tt class="docutils literal">$ <span class="pre">./color_maker_top-syn.sh</span></tt></div>
</div>
<p>In order to successfully run the entire process, you should have the target
board connected to the host and it should be powered on.</p>
<p>The synthesis procedure invokes several Xilinx ISE command-line tools for logic
synthesis as described in the corresponding Makefile, found in the
the <tt class="docutils literal"><span class="pre">color_maker-s3esk</span></tt> directory.</p>
<p>Typically, this process includes the following:</p>
<ul class="simple">
<li>Generation of the <tt class="docutils literal">*.xst</tt> synthesis script file.</li>
<li>Generation of the <tt class="docutils literal">*.ngc</tt> gate-level netlist file in NGC format.</li>
<li>Building the corresponding <tt class="docutils literal">*.ngd</tt> file.</li>
<li>Performing mapping using <tt class="docutils literal">map</tt> which generates the corresponding <tt class="docutils literal">*.ncd</tt>
file.</li>
<li>Place-and-routing using <tt class="docutils literal">par</tt> which updates the corresponding <tt class="docutils literal">*.ncd</tt>
file.</li>
<li>Tracing critical paths using <tt class="docutils literal">trce</tt> for reoptimizing the <tt class="docutils literal">*.ncd</tt> file.</li>
<li>Bitstream generation (<tt class="docutils literal">*.bit</tt>) using <tt class="docutils literal">bitgen</tt>, however with unused pins.</li>
</ul>
<p>As a result of this process, the <tt class="docutils literal">color_maker_top.bit</tt> bitstream file is
produced.</p>
<p>Then, the shell script invokes the Xilinx IMPACT tool by a Windows batch file,
automatically passing a series of commands that are necessary for configuring
the target FPGA device:</p>
<ol class="arabic simple">
<li>Set mode to binary scan.</li>
</ol>
<div class="line-block">
<div class="line"><tt class="docutils literal">setMode <span class="pre">-bs</span></tt></div>
</div>
<ol class="arabic simple" start="2">
<li>Set cable port detection to auto (tests various ports).</li>
</ol>
<div class="line-block">
<div class="line"><tt class="docutils literal">setCable <span class="pre">-p</span> auto</tt></div>
</div>
<ol class="arabic simple" start="3">
<li>Identify parts and their order in the scan chain.</li>
</ol>
<div class="line-block">
<div class="line"><tt class="docutils literal">identify</tt></div>
</div>
<ol class="arabic simple" start="4">
<li>Assign the bitstream to the first part in the scan chain.</li>
</ol>
<div class="line-block">
<div class="line"><tt class="docutils literal">assignFile <span class="pre">-p</span> 1 <span class="pre">-file</span> color_maker_top.bit</tt></div>
</div>
<ol class="arabic simple" start="5">
<li>Program the selected device.</li>
</ol>
<div class="line-block">
<div class="line"><tt class="docutils literal">program <span class="pre">-p</span> 1</tt></div>
</div>
<ol class="arabic simple" start="6">
<li>Exit IMPACT.</li>
</ol>
<div class="line-block">
<div class="line"><tt class="docutils literal">exit</tt></div>
</div>
</div>
</div>
<div class="section" id="prerequisites">
<h1>4. Prerequisites</h1>
<ul class="simple">
<li>[suggested] Linux (e.g., Ubuntu 16.04 LTS) or MinGW environment on Windows 7 (64-bit).</li>
<li>[suggested] GHDL simulator: <a class="reference external" href="http://ghdl.free.fr">http://ghdl.free.fr</a>
The 0.33 version on Linux Ubuntu 16.04 LTS was used.</li>
<li>[optional] The VGA simulator: <a class="reference external" href="http://ericeastwood.com/lab/vga-simulator/">http://ericeastwood.com/lab/vga-simulator/</a></li>
<li>Xilinx ISE (free ISE webpack is available from the Xilinx website):
<a class="reference external" href="http://www.xilinx.com">http://www.xilinx.com</a>.
The 14.6 version on Windows 7/64-bit is known to work.</li>
</ul>
</div>
</div>
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