vivado xsim support for xci or xilinx ip

[skokvermon]

Hi,
it seems that vivado xsim doesn't support generating xilinx ip for simulation.
It is supported for synthesis

Is it a planned feature?
If not I would be willing to help implementing it.

[Jbalkind]

I think we'd all love to see that if you're willing to give it a go :)

[olofk]

Yes, that is a known issue. Currently, the vivado backend runs in project mode while xsim runs in non-project mode. My proposal is to convert the xsim backend to run in project mode as well. That should bring a number of other features as well. Haven't got the bandwidth to work on it myself so very happy for any help here.

[skokvermon]

xsim doesn't launch vivado at all. It only calls xelab and xsim.
xci and other ip should not be related to xsim, as it only implies code generation.
Also xilinx ip generation could be used in other simulators.

It could be treated as a dependency, or any other code generation flow. Is there such framework in fusesoc?

[skokvermon]

I implemented a working solution which should be compatible with synthesis.
I could make a working fusesoc simulation of xilinx example ddr bench.

I still have to test synthesis and will release it.

In my case, I'm using mig memories, which are entirely described in "mig_a.prj" file. xci file is not needed for these, and ip can be created using 3 lines of tcl:

create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name myMig
set_property -dict [list CONFIG.XML_INPUT_FILE {xci/mig_a.prj}] [get_ips myMig]
generate_target simulation [ get_files *.xci ]

This will generate myMig Module. this xml file is quite compact and should be easily hand edited.
xci file contains no needed information for mig ips.
May I propose to use a new_file_type "mig", which would generate mig ips only with this prj file?
this has to be done also in vivado.py for synthesis of course.

implementation is quite easy thanks to jinja templates

[skokvermon]

pull request made
#377
Sorry for the delay