-
Notifications
You must be signed in to change notification settings - Fork 97
/
p9_mss_eff_grouping.C
2956 lines (2567 loc) · 111 KB
/
p9_mss_eff_grouping.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///----------------------------------------------------------------------------
/// @file p9_mss_eff_grouping.C
///
/// @brief Perform Memory Controller grouping on a processor chip
///
/// The purpose of this procedure is to effectively group the memory on each
/// processor chip based on available memory behind its memory grouping ports.
/// Some placement policy/scheme and other info that are stored in the
/// attributes are used as part of the grouping process.
///
///----------------------------------------------------------------------------
/// *HWP HWP Owner : Joe McGill <jmcgill@us.ibm.com>
/// *HWP FW Owner : Thi Tran <thi@us.ibm.com>
/// *HWP Team : Nest
/// *HWP Level : 3
/// *HWP Consumed by : HB
///----------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
#include <p9_mss_eff_grouping.H>
#include <p9_fbc_utils.H>
#include <map>
#include <generic/memory/lib/utils/memory_size.H>
///----------------------------------------------------------------------------
/// Constant definitions
///----------------------------------------------------------------------------
// ------------------
// System structure
// ------------------
// MC port position
const uint8_t MCPORTID_0 = 0x0;
const uint8_t MCPORTID_1 = 0x1;
const uint8_t MCPORTID_2 = 0x2;
const uint8_t MCPORTID_3 = 0x3;
const uint8_t MCPORTID_4 = 0x4;
const uint8_t MCPORTID_5 = 0x5;
const uint8_t MCPORTID_6 = 0x6;
const uint8_t MCPORTID_7 = 0x7;
// Max queues per port (MCPERF0 16:21)
const uint8_t MAX_HTM_QUEUE_PER_PORT = 16;
// -----------------------
// Group allow definitions
// -----------------------
// Enum value used to decode ATTR_MSS_INTERLEAVE_ENABLE
// P9 allows 1, 2, 3, 4, 6, or 8 memory ports to be grouped together.
enum GroupAllowed
{
GROUP_1 = 0b00000001, // 0x01 Group of 1 port allowed
GROUP_2 = 0b00000010, // 0x02 Group of 2 ports allowed
GROUP_3 = 0b00000100, // 0x04 Group of 3 ports allowed
GROUP_4 = 0b00001000, // 0x08 Group of 4 ports allowed
GROUP_6 = 0b00100000, // 0x20 Group of 6 ports allowed
GROUP_8 = 0b10000000, // 0x80 Group of 8 ports allowed
ALL_GROUPS = GROUP_1 |
GROUP_2 |
GROUP_3 |
GROUP_4 |
GROUP_6 |
GROUP_8,
};
///----------------------------------------------------------------------------
/// struct EffGroupingSysAttrs
///----------------------------------------------------------------------------
///
/// @struct EffGroupingSysAttrs
/// Contains system attribute values that are needed to perform
/// memory effective grouping.
///
struct EffGroupingSysAttrs
{
///
/// @brief getAttrs
/// Function that reads the system attributes and load their values
/// into the struct.
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode getAttrs();
// Public data
uint8_t iv_selectiveMode = 0; // ATTR_MEM_MIRROR_PLACEMENT_POLICY
uint8_t iv_hwMirrorEnabled = 0; // ATTR_MRW_HW_MIRRORING_ENABLE
uint8_t iv_groupsAllowed = 0; // ATTR_MSS_INTERLEAVE_ENABLE
};
// See doxygen in struct definition.
fapi2::ReturnCode EffGroupingSysAttrs::getAttrs()
{
FAPI_DBG("Entering EffGroupingSysAttrs::getAttrs");
fapi2::ReturnCode l_rc;
const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
// Get mirror placement policy
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY,
FAPI_SYSTEM, iv_selectiveMode),
"Error getting ATTR_MEM_MIRROR_PLACEMENT_POLICY, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Get mirror option
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MRW_HW_MIRRORING_ENABLE,
FAPI_SYSTEM, iv_hwMirrorEnabled),
"Error getting ATTR_MRW_HW_MIRRORING_ENABLE, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Get interleave option
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_INTERLEAVE_ENABLE, FAPI_SYSTEM,
iv_groupsAllowed),
"Error getting ATTR_MSS_INTERLEAVE_ENABLE, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Display attribute values
FAPI_INF("EffGroupingSysAttrs: ");
FAPI_INF(" ATTR_MEM_MIRROR_PLACEMENT_POLICY 0x%.8X", iv_selectiveMode);
FAPI_INF(" ATTR_MRW_HW_MIRRORING_ENABLE 0x%.8X", iv_hwMirrorEnabled);
FAPI_INF(" ATTR_MSS_INTERLEAVE_ENABLE 0x%.8X", iv_groupsAllowed);
fapi_try_exit:
FAPI_DBG("Exiting EffGroupingSysAttrs::getAttrs");
return fapi2::current_err;
}
///----------------------------------------------------------------------------
/// struct EffGroupingProcAttrs
///----------------------------------------------------------------------------
///
/// @struct EffGroupingProcAttrs
/// Contains processor chip attribute values that are needed to perform
/// memory effective grouping.
///
struct EffGroupingProcAttrs
{
///
/// @brief getAttrs
/// Function that reads the processor target attributes and load their
/// values into the struct.
///
/// @param[in] i_target Reference to processor chip target
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode getAttrs(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const EffGroupingSysAttrs i_sysAttrs);
///
/// @brief calcProcBaseAddr
/// Function that calculates the Memory base address values (for both
/// non-mirrored/mirrored memory) for this proc target.
/// The memory base addresses then will be written to the
/// ATTR_PROC_MEM_BASE and ATTR_PROC_MIRROR_BASE attributes.
///
/// @param[in] i_target Reference to processor chip target
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode calcProcBaseAddr(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const EffGroupingSysAttrs i_sysAttrs);
// Public data
uint64_t iv_memBaseAddr = 0; // ATTR_PROC_MEM_BASE
uint64_t iv_mirrorBaseAddr = 0; // ATTR_PROC_MIRROR_BASE
uint64_t iv_nhtmBarSize; // ATTR_PROC_NHTM_BAR_SIZE
uint64_t iv_chtmBarSizes[NUM_OF_CHTM_REGIONS]; // ATTR_PROC_CHTM_BAR_SIZES
uint64_t iv_occSandboxSize = 0; // ATTR_PROC_OCC_SANDBOX_SIZE
uint32_t iv_fabricSystemId = 0; // ATTR_PROC_FABRIC_SYSTEM_ID
uint8_t iv_fabricGroupId = 0; // ATTR_PROC_FABRIC_GROUP_ID
uint8_t iv_fabricChipId = 0; // ATTR_PROC_FABRIC_CHIP_ID
};
// See doxygen in struct definition.
fapi2::ReturnCode EffGroupingProcAttrs::calcProcBaseAddr(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const EffGroupingSysAttrs i_sysAttrs)
{
FAPI_DBG("Entering");
fapi2::ReturnCode l_rc;
uint64_t l_memBaseAddr1, l_mmioBaseAddr;
// Get the Mirror/Non-mirror base addresses
FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
EFF_FBC_GRP_CHIP_IDS,
iv_memBaseAddr,
l_memBaseAddr1,
iv_mirrorBaseAddr,
l_mmioBaseAddr),
"p9_fbc_utils_get_chip_base_address() returns an error, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Write base addr for non-mirror memory regions
FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_MEM_BASE, i_target,
iv_memBaseAddr),
"Error setting ATTR_PROC_MEM_BASE, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Set base addr for mirror memory regions
FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_MIRROR_BASE, i_target,
iv_mirrorBaseAddr),
"Error setting ATTR_PROC_MIRROR_BASE, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
fapi_try_exit:
FAPI_DBG("Exiting");
return fapi2::current_err;
}
// See doxygen in struct definition.
fapi2::ReturnCode EffGroupingProcAttrs::getAttrs(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const EffGroupingSysAttrs i_sysAttrs)
{
FAPI_DBG("Entering EffGroupingProcAttrs::getAttrs");
fapi2::ReturnCode l_rc;
// Get Nest Hardware Trace Macro (NHTM) bar size
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NHTM_BAR_SIZE, i_target, iv_nhtmBarSize),
"Error getting ATTR_PROC_HTM_BAR_SIZE, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Get Core Hardware Trace Macro (CHTM) bar size
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_CHTM_BAR_SIZES, i_target, iv_chtmBarSizes),
"Error getting ATTR_PROC_CHTM_BAR_SIZES, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Get On Chip Controler (OCC) sandbox size
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_OCC_SANDBOX_SIZE, i_target,
iv_occSandboxSize),
"Error getting ATTR_PROC_OCC_SANDBOX_SIZE, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Get Fabric system ID
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target,
iv_fabricSystemId),
"Error getting ATTR_PROC_FABRIC_SYSTEM_ID, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Get Fabric group ID
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target,
iv_fabricGroupId),
"Error getting ATTR_PROC_FABRIC_GROUP_ID, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Get Fabric chip ID
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target,
iv_fabricChipId),
"Error getting ATTR_PROC_FABRIC_CHIP_ID, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Figure out memory base addresses for this proc and
// writes values to ATTR_PROC_MEM_BASE and ATTR_PROC_MIRROR_BASE
FAPI_TRY(calcProcBaseAddr(i_target, i_sysAttrs),
"EffGroupingProcAttrs::getAttrs: calcProcBaseAddr() returns "
"error, l_rc 0x%.8X", (uint64_t)fapi2::current_err);
// Display attribute values
FAPI_INF("EffGroupingProcAttrs::getAttrs: ");
FAPI_INF(" ATTR_PROC_NHTM_BAR_SIZE 0x%.16llX", iv_nhtmBarSize);
for (uint8_t ii = 0; ii < NUM_OF_CHTM_REGIONS; ii++)
{
FAPI_INF(" ATTR_PROC_CHTM_BAR_SIZES[%u] 0x%.16llX", ii, iv_chtmBarSizes[ii]);
}
FAPI_INF(" ATTR_PROC_OCC_SANDBOX_SIZE 0x%.16llX", iv_occSandboxSize);
FAPI_INF(" ATTR_PROC_FABRIC_SYSTEM_ID 0x%.8X", iv_fabricSystemId);
FAPI_INF(" ATTR_PROC_FABRIC_GROUP_ID 0x%.8X", iv_fabricGroupId);
FAPI_INF(" ATTR_PROC_FABRIC_CHIP_ID 0x%.8X", iv_fabricChipId);
FAPI_INF(" ATTR_PROC_MEM_BASE 0x%.16llX", iv_memBaseAddr);
FAPI_INF(" ATTR_PROC_MIRROR_BASE 0x%.16llX", iv_mirrorBaseAddr);
fapi_try_exit:
FAPI_DBG("Exiting EffGroupingProcAttrs::getAttrs");
return fapi2::current_err;
}
///----------------------------------------------------------------------------
/// struct EffGroupingMcaAttrs
///----------------------------------------------------------------------------
///
/// @struct EffGroupingMcaAttrs
///
/// Contains attributes for an MCA Chiplet (Nimbus only)
///
struct EffGroupingMcaAttrs
{
///
/// @brief Getting attribute of an MCA chiplet
///
/// Function that reads the MCA target attributes and load their
/// values into the struct.
///
/// @param[in] i_target Reference to MCA chiplet target
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode getAttrs(
const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target);
// Unit Position
uint8_t iv_unitPos = 0;
// Dimm size behind this MCA
uint64_t iv_dimmSize = 0;
};
// See doxygen in struct definition.
fapi2::ReturnCode EffGroupingMcaAttrs::getAttrs(
const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target)
{
FAPI_DBG("Entering EffGroupingMcaAttrs::getAttrs");
fapi2::ReturnCode l_rc;
// Get the amount of memory behind this MCA target
// Note: DIMM must be enabled to be accounted for.
FAPI_TRY(mss::eff_memory_size(i_target, iv_dimmSize),
"Error returned from eff_memory_size, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Get the MCA unit position
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, iv_unitPos),
"Error getting MCA ATTR_CHIP_UNIT_POS, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// MCA's total dimm size
FAPI_INF("MCA %u: Total DIMM size %lu GB", iv_unitPos, iv_dimmSize);
fapi_try_exit:
FAPI_DBG("Exiting EffGroupingMcaAttrs::getAttrs");
return fapi2::current_err;
}
///----------------------------------------------------------------------------
/// struct EffGroupingDmiAttrs
///----------------------------------------------------------------------------
///
/// @struct EffGroupingDmiAttrs
///
/// Contains attributes for an DMI Chiplet (Cumulus only)
///
struct EffGroupingDmiAttrs
{
///
/// @brief Getting attribute of a DMI chiplet
///
/// Function that reads the DMI target attributes and load their
/// values into the struct.
///
/// @param[in] i_target Reference to DMI chiplet target
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode getAttrs(
const fapi2::Target<fapi2::TARGET_TYPE_DMI>& i_target);
// Unit Position
uint8_t iv_unitPos = 0;
// Dimm size behind this DMI
uint64_t iv_dimmSize = 0;
// The membuf chip associated with this DMI
// (for deconfiguring if cannot group)
fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> iv_membuf;
};
// See doxygen in struct definition.
fapi2::ReturnCode EffGroupingDmiAttrs::getAttrs(
const fapi2::Target<fapi2::TARGET_TYPE_DMI>& i_target)
{
FAPI_DBG("Entering EffGroupingDmiAttrs::getAttrs");
fapi2::ReturnCode l_rc;
// Get the membuf attached to this DMI
auto l_attachedMembuf = i_target.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>();
if (l_attachedMembuf.size() > 0)
{
// Set the membuf associated with this DMI, supposed to be only 1
// Centaur per DMI
iv_membuf = l_attachedMembuf.front();
// Get the amount of memory behind this DMI target
FAPI_TRY(mss::eff_memory_size(i_target, iv_dimmSize),
"Error returned from eff_memory_size, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
}
// Get the DMI unit position
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, iv_unitPos),
"Error getting DMI ATTR_CHIP_UNIT_POS, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Display this DMI's attribute info
FAPI_INF("EffGroupingDmiAttrs::getAttrs: DMI %d, Centaur attached %d, "
"iv_dimmSize %d GB ",
iv_unitPos, l_attachedMembuf.size(), iv_dimmSize);
fapi_try_exit:
FAPI_DBG("Exiting EffGroupingDmiAttrs::getAttrs");
return fapi2::current_err;
}
///----------------------------------------------------------------------------
/// struct EffGroupingMemInfo
///----------------------------------------------------------------------------
///
/// @struct EffGroupingMemInfo
/// Contains Memory Information for a processor chip.
///
/// Nimbus - 4 MCS total, 2 MCA ports per MCS, 2 DIMMSs per MCA port
///
/// MCS0 --> MCA port0 --> DIMM0
/// DIMM1
/// MCA port1 --> DIMM0
/// DIMM1
/// MCS1 --> MCA port2 --> DIMM0
/// DIMM1
/// MCA port3 --> DIMM0
/// DIMM1
/// MCS2 --> MCA port4 --> DIMM0
/// DIMM1
/// MCA port5 --> DIMM0
/// DIMM1
/// MCS3 --> MCA port6 --> DIMM0
/// DIMM1
/// MCA port7 --> DIMM0
/// DIMM1
/// ----------------------------
/// Total 4 8
///
///
/// Cumulus - 4 MIs total, each MI has 2 DMIs (MC ports) with memBufs
/// connected.
/// Each memBuf has 2 MBAs, each MBA has 2 DRAM ports, each
/// DRAM port has 2 DIMMs
///
/// MI0 --> DMI0 --> memBuf --> MBA01 --> Port0 --> DIMM0
/// DIMM1
/// Port1 --> DIMM0
/// DIMM1
/// MBA23 --> Port2 --> DIMM0
/// DIMM1
/// Port3 --> DIMM0
/// DIMM1
///
/// DMI1 --> memBuf --> MBA01 --> Port0 --> DIMM0
/// DIMM1
/// Port1 --> DIMM0
/// DIMM1
/// MBA23 --> Port2 --> DIMM0
/// DIMM1
/// Port3 --> DIMM0
/// DIMM1
/// ......
/// ......
///
/// MI3 --> DMI6 --> memBuf --> MBA01 --> Port0 --> DIMM0
/// DIMM1
/// Port1 --> DIMM0
/// DIMM1
/// MBA23 --> Port2 --> DIMM0
/// DIMM1
/// Port3 --> DIMM0
/// DIMM1
///
/// DMI7 --> memBuf --> MBA01 --> Port0 --> DIMM0
/// DIMM1
/// Port1 --> DIMM0
/// DIMM1
/// MBA23 --> Port2 --> DIMM0
/// DIMM1
/// Port3 --> DIMM0
/// DIMM1
/// ----------------------------------------------------------------
/// Total 4 8
///
struct EffGroupingMemInfo
{
// Constructor
EffGroupingMemInfo()
{
memset(iv_portSize, 0, sizeof(iv_portSize));
}
///
/// @brief Gets the memory information of a processor
///
/// @param[in] i_target Reference to processor chip target
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode getMemInfo(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
// Mark if this proc is a Nimbus
bool iv_nimbusProc = false;
// Memory sizes behind MC ports
uint32_t iv_portSize[NUM_MC_PORTS_PER_PROC];
};
// See doxygen in struct definition.
fapi2::ReturnCode EffGroupingMemInfo::getMemInfo (
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
FAPI_DBG("Entering");
fapi2::ReturnCode l_rc;
// Memory info will be filled in differently for Nimbus vs Cumulus
// due to chip structure
// Get the functional MCAs
auto l_mcaChiplets = i_target.getChildren<fapi2::TARGET_TYPE_MCA>();
if (l_mcaChiplets.size() > 0)
{
FAPI_DBG("Number of MCAs found: %d", l_mcaChiplets.size());
// MCA found, proc is a Nimbus.
iv_nimbusProc = true;
for (auto l_mca : l_mcaChiplets)
{
// Get the MCA attributes
EffGroupingMcaAttrs l_mcaAttrs;
FAPI_TRY(l_mcaAttrs.getAttrs(l_mca),
"l_mcaAttrs.getAttrs() returns error, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Get the mem size behind this MCA
iv_portSize[l_mcaAttrs.iv_unitPos] = l_mcaAttrs.iv_dimmSize;
}
}
else
{
auto l_dmiChiplets = i_target.getChildren<fapi2::TARGET_TYPE_DMI>();
if (l_dmiChiplets.size() > 0)
{
FAPI_DBG("Number of DMIs found: %d", l_dmiChiplets.size());
// DMI found, proc is a Cumulus.
for (auto l_dmi : l_dmiChiplets)
{
// Get this DMI attribute info
EffGroupingDmiAttrs l_dmiAttrs;
FAPI_TRY(l_dmiAttrs.getAttrs(l_dmi),
"l_dmiAttrs.getAttrs() returns error, l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
// Fill in memory info
iv_portSize[l_dmiAttrs.iv_unitPos] = l_dmiAttrs.iv_dimmSize;
}
}
else
{
// Note: You may have none of DMI nor MCA but it's a valid state;
// therefore don't flag an error
FAPI_INF("No MCA or DMI found in this proc target");
}
}
// Display amount of memory for each MC port
for (uint8_t ii = 0; ii < NUM_MC_PORTS_PER_PROC; ii++)
{
FAPI_INF("MCport[%d] = %d GB", ii, iv_portSize[ii]);
}
fapi_try_exit:
FAPI_DBG("Exiting");
return fapi2::current_err;
}
///----------------------------------------------------------------------------
/// struct EffGroupingMemInfo
///----------------------------------------------------------------------------
///
/// @struct EffGroupingData
/// Contains Effective Grouping Data for a processor chip.
///
struct EffGroupingData
{
// Constructor
EffGroupingData()
{
memset(iv_data, 0, sizeof(iv_data));
for (uint8_t l_port = 0; l_port < NUM_MC_PORTS_PER_PROC; l_port++)
{
iv_portGrouped[l_port] = false;
}
}
// The ATTR_MSS_MCS_GROUP_32 attribute
uint32_t iv_data[DATA_GROUPS][DATA_ELEMENTS];
// The ports that have been grouped
bool iv_portGrouped[NUM_MC_PORTS_PER_PROC];
// The number of groups
uint8_t iv_numGroups = 0;
// The total non-mirrored memory size in GB
uint32_t iv_totalSizeNonMirr = 0;
};
///----------------------------------------------------------------------------
/// struct EffGroupingBaseSizeData
///----------------------------------------------------------------------------
struct EffGroupingBaseSizeData
{
// Constructor
EffGroupingBaseSizeData()
{
memset(iv_mem_bases, 0, sizeof(iv_mem_bases));
memset(iv_mem_bases_ack, 0, sizeof(iv_mem_bases_ack));
memset(iv_memory_sizes, 0, sizeof(iv_memory_sizes));
memset(iv_memory_sizes_ack, 0, sizeof(iv_memory_sizes_ack));
memset(iv_mirror_bases, 0, sizeof(iv_mirror_bases));
memset(iv_mirror_bases_ack, 0, sizeof(iv_mirror_bases_ack));
memset(iv_mirror_sizes, 0, sizeof(iv_mirror_sizes));
memset(iv_mirror_sizes_ack, 0, sizeof(iv_mirror_sizes_ack));
memset(iv_chtm_bar_bases, 0, sizeof(iv_chtm_bar_bases));
memset(iv_numHtmQueues, 0, sizeof(iv_numHtmQueues));
}
///
/// @brief setBaseSizeData
/// Function that set base and size values for both mirror
/// and non-mirror.
///
/// @param[in] i_sysAttrs System attribute settings
/// @param[in] i_groupData Effective grouping data info
///
/// @return void.
///
void setBaseSizeData(const EffGroupingSysAttrs& i_sysAttrs,
const EffGroupingData& i_groupData);
///
/// @brief Figure out which memory region (index) an address belongs to.
///
/// @param[in] i_addr Given address
/// @param[in] i_sysAttrs System attribute settings
/// @param[out] o_accMemSize Accumulated memory size to cover address
///
/// @return Memory region index where i_addr belongs to.
///
uint8_t getMemoryRegionIndex(const uint64_t i_addr,
const EffGroupingSysAttrs& i_sysAttrs,
uint64_t& o_accMemSize);
///
/// @brief Calculate then assign the number of HTM queues for each
/// channel. This is done for performance purpose when dumping
/// out HTM traces.
///
/// @param[in] i_groupData Effective grouping data info
/// @param[in] i_startHtmIndex Start HTM group index
/// @param[in] i_endHtmIndex End HTM group index
///
/// @return void
///
void calcHtmQueues(const EffGroupingData& i_groupData,
const uint64_t i_startHtmIndex,
const uint64_t i_endHtmIndex);
// Calculate # of HTM queues to be reserved
// To improve trace performance, we need to reserve HTM queues on
// the channels that serve HTM trace space.
// The # of queues will be 16 (maximum) divided by the # of ports
///
/// @brief Setting HTM and OCC base address based on HTM/OCC bar size
///
/// @param[in] i_target Reference to Processor Chip Target
/// @param[in] i_sysAttrs System attribute settings
/// @param[in] i_groupData Effective grouping data info
/// @param[in] i_procAttrs Proc attribute values
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode set_HTM_OCC_base_addr(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const EffGroupingSysAttrs& i_sysAttrs,
const EffGroupingData& i_groupData,
const EffGroupingProcAttrs& i_procAttrs);
///
/// @brief setBaseSizeAttr
/// Function that set base and size attribute values for both mirror
/// and non-mirror based on given base/size data.
///
/// @param[in] i_target Reference to Processor Chip Target
/// @param[in] i_sysAttrs System attribute settings
/// @param[in/out] i_groupData Effective grouping data info
///
/// @return FAPI2_RC_SUCCESS if success, else error code.
///
fapi2::ReturnCode setBaseSizeAttr(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const EffGroupingSysAttrs& i_sysAttrs,
EffGroupingData& io_groupData);
// Public data
uint64_t iv_mem_bases[NUM_NON_MIRROR_REGIONS];
uint64_t iv_mem_bases_ack[NUM_NON_MIRROR_REGIONS];
uint64_t iv_memory_sizes[NUM_NON_MIRROR_REGIONS];
uint64_t iv_memory_sizes_ack[NUM_NON_MIRROR_REGIONS];
uint64_t iv_mirror_bases[NUM_MIRROR_REGIONS];
uint64_t iv_mirror_bases_ack[NUM_MIRROR_REGIONS];
uint64_t iv_mirror_sizes[NUM_MIRROR_REGIONS];
uint64_t iv_mirror_sizes_ack[NUM_MIRROR_REGIONS];
uint64_t iv_occ_sandbox_base = 0;
uint64_t iv_nhtm_bar_base = 0;
uint64_t iv_chtm_bar_bases[NUM_OF_CHTM_REGIONS];
// Num of HTM queues to be reserved for each port
uint8_t iv_numHtmQueues[NUM_MC_PORTS_PER_PROC];
};
// See description in struct definition
void EffGroupingBaseSizeData::setBaseSizeData(
const EffGroupingSysAttrs& i_sysAttrs,
const EffGroupingData& i_groupData)
{
FAPI_DBG("Entering");
// Process non-mirrored ranges
for (uint8_t ii = 0; ii < (DATA_GROUPS / 2); ii++) // 0-7 --> Non mirror
{
// Base addresses for distinct non-mirrored ranges
iv_mem_bases[ii] = i_groupData.iv_data[ii][BASE_ADDR];
iv_mem_bases_ack[ii] = i_groupData.iv_data[ii][BASE_ADDR];
iv_memory_sizes[ii] = i_groupData.iv_data[ii][PORT_SIZE] *
i_groupData.iv_data[ii][PORTS_IN_GROUP];
iv_memory_sizes_ack[ii] = i_groupData.iv_data[ii][GROUP_SIZE];
// Convert to full byte addresses
iv_mem_bases[ii] <<= 30;
iv_mem_bases_ack[ii] <<= 30;
iv_memory_sizes[ii] <<= 30;
iv_memory_sizes_ack[ii] <<= 30;
FAPI_DBG("Non-mirror, Group %d:", ii);
FAPI_DBG(" i_groupData.iv_data[%d][BASE_ADDR] = %d",
ii, i_groupData.iv_data[ii][BASE_ADDR]);
FAPI_DBG(" i_groupData.iv_data[%d][PORT_SIZE] = %d",
ii, i_groupData.iv_data[ii][PORT_SIZE]);
FAPI_DBG(" i_groupData.iv_data[%d][PORTS_IN_GROUP] = %d",
ii, i_groupData.iv_data[ii][PORTS_IN_GROUP]);
FAPI_DBG(" iv_mem_bases[%d] = 0x%.16llX (%d GB)",
ii, iv_mem_bases[ii], iv_mem_bases[ii] >> 30);
FAPI_DBG(" iv_mem_bases_ack[%d] = 0x%.16llX (%d GB)",
ii, iv_mem_bases_ack[ii], iv_mem_bases_ack[ii] >> 30);
FAPI_DBG(" iv_memory_sizes[%d] = %.16lld bytes (%d GB)",
ii, iv_memory_sizes[ii], iv_memory_sizes[ii] >> 30);
FAPI_DBG(" iv_memory_sizes_ack[%d] = %.16lld bytes (%d GB)",
ii, iv_memory_sizes_ack[ii], iv_memory_sizes_ack[ii] >> 30);
}
// Process mirrored ranges
if (i_sysAttrs.iv_hwMirrorEnabled)
{
for (uint8_t ii = 0; ii < NUM_MIRROR_REGIONS; ii++)
{
uint8_t l_index = ii + MIRR_OFFSET;
// Set base address for distinct mirrored ranges
iv_mirror_bases[ii] = i_groupData.iv_data[l_index][BASE_ADDR];
iv_mirror_bases_ack[ii] = i_groupData.iv_data[l_index][BASE_ADDR];
// Set sizes for distinct mirrored ranges
if (i_groupData.iv_data[ii][PORTS_IN_GROUP] > 1) // ii -> Non-mirror index
{
iv_mirror_sizes[ii] = (i_groupData.iv_data[ii][PORT_SIZE] *
i_groupData.iv_data[ii][PORTS_IN_GROUP]) / 2;
}
iv_mirror_sizes_ack[ii] = i_groupData.iv_data[l_index][GROUP_SIZE];
// Convert to full byte addresses
iv_mirror_bases[ii] <<= 30;
iv_mirror_bases_ack[ii] <<= 30;
iv_mirror_sizes[ii] <<= 30;
iv_mirror_sizes_ack[ii] <<= 30;
FAPI_DBG("Mirror: %d", ii);
FAPI_DBG(" i_groupData.iv_data[%d][BASE_ADDR] = 0x%.16llX (%d GB)",
l_index, i_groupData.iv_data[l_index][BASE_ADDR],
i_groupData.iv_data[l_index][BASE_ADDR] >> 30);
FAPI_DBG(" i_groupData.iv_data[%d][PORTS_IN_GROUP] = %d",
l_index, i_groupData.iv_data[l_index][PORTS_IN_GROUP]);
FAPI_DBG(" i_groupData.iv_data[%d][PORT_SIZE] = %d",
l_index, i_groupData.iv_data[l_index][PORT_SIZE]);
FAPI_DBG(" iv_mirror_bases[%d] = 0x%.16llX (%d GB)",
ii, iv_mirror_bases[ii], iv_mirror_bases[ii] >> 30);
FAPI_DBG(" iv_mirror_bases_ack[%d] = 0x%.16llX (%d GB)",
ii, iv_mirror_bases_ack[ii], iv_mirror_bases_ack[ii] >> 30);
FAPI_DBG(" iv_mirror_sizes[%d] = %.16lld bytes (%d GB)",
ii, iv_mirror_sizes[ii], iv_mirror_sizes[ii] >> 30);
FAPI_DBG(" iv_mirror_sizes_ack[%d] = %.16lld bytes (%d GB)",
ii, iv_mirror_sizes_ack[ii], iv_mirror_sizes_ack[ii] >> 30);
}
}
FAPI_DBG("Exiting");
return;
}
// See description in struct definition
uint8_t EffGroupingBaseSizeData::getMemoryRegionIndex(
const uint64_t i_addr,
const EffGroupingSysAttrs& i_sysAttrs,
uint64_t& o_accMemSize)
{
uint8_t l_index = 0xFF;
uint8_t l_numRegions = 0;
uint64_t* l_memSizePtr = NULL;
uint64_t l_startBaseAddr = 0;
FAPI_DBG("Entering EffGroupingBaseSizeData::getMemoryRegionIndex: "
"i_addr = %.16lld bytes (%d GB)", i_addr, i_addr >> 30);
// Point to non-mirror or mirror memory data
l_memSizePtr = &iv_memory_sizes[0];
l_numRegions = NUM_NON_MIRROR_REGIONS;
l_startBaseAddr = iv_mem_bases[0];
if (i_sysAttrs.iv_selectiveMode ==
fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED)
{
l_memSizePtr = &iv_mirror_sizes[0] ;
l_numRegions = NUM_MIRROR_REGIONS;
l_startBaseAddr = iv_mirror_bases[0];
}
FAPI_DBG(" Start base addr: %.16lld (%d GB), Num regions %d",
l_startBaseAddr, l_startBaseAddr >> 30, l_numRegions);
o_accMemSize = 0;
for (uint8_t ii = 0; ii < l_numRegions; ii++)
{
// If mem available in region, add them up
if ( (*l_memSizePtr) > 0 )
{
o_accMemSize += (*l_memSizePtr);
FAPI_DBG("ii = %d, o_accMemSize = %.16lld (%d GB)",
ii, o_accMemSize, o_accMemSize >> 30);
if ( (l_startBaseAddr + o_accMemSize) >= i_addr )
{
l_index = ii;
break;
}
}
// Passed last region (no more memory). This is the case where
// ALT_MEM exists, just return highest region index that contains memory.
else
{
l_index = ii - 1;
break;
}
// Point to next region
l_memSizePtr++;
}
FAPI_INF("Exiting - Index = %d, , o_accAddrValue = %.16lld (%d GB)",
l_index, o_accMemSize, o_accMemSize >> 30);
return l_index;
}
// See description in struct definition
void EffGroupingBaseSizeData::calcHtmQueues(const EffGroupingData& i_groupData,
const uint64_t i_startHtmIndex,
const uint64_t i_endHtmIndex)
{
// To improve trace performance, we need to reserve HTM queues on
// the channels that serve HTM trace space.
// Number of ports from HTM start -> HTM end
uint8_t l_totalPorts = 0;
for (uint8_t ii = i_startHtmIndex; ii <= i_endHtmIndex; ii++)
{
l_totalPorts += i_groupData.iv_data[ii][PORTS_IN_GROUP];
}
// Spread the queues evenly to all the ports that serve HTM
// Each will have max queues (16) divided by the # of ports
uint8_t l_numQueues = MAX_HTM_QUEUE_PER_PORT / l_totalPorts;
FAPI_DBG("l_totalPorts = %d, l_numQueues %d", l_totalPorts, l_numQueues);
// Set the queues to the port array
for (uint8_t ii = i_startHtmIndex; ii <= i_endHtmIndex; ii++)
{
// Ports in group loop
for (uint8_t l_memberIdx = 0;
l_memberIdx < i_groupData.iv_data[ii][PORTS_IN_GROUP]; l_memberIdx++)
{
uint8_t jj = i_groupData.iv_data[ii][MEMBER_IDX(0) + l_memberIdx];
iv_numHtmQueues[jj] = l_numQueues;
}
}
return;
}
// See description in struct definition
fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const EffGroupingSysAttrs& i_sysAttrs,
const EffGroupingData& i_groupData,
const EffGroupingProcAttrs& i_procAttrs)
{
FAPI_DBG("Entering");
fapi2::ReturnCode l_rc;
// Hold mem bases & sizes for mirror/non-mirror
uint8_t l_numRegions = 0;
uint64_t l_mem_bases[NUM_NON_MIRROR_REGIONS];
uint64_t l_mem_sizes[NUM_NON_MIRROR_REGIONS];
uint64_t l_totalSize = 0;
uint8_t l_memHole = 0;
uint8_t l_index = 0;
uint64_t l_accMemSize = 0;
uint64_t l_memSizeAfterHtmOcc = 0;
bool l_firstEnabledChtm = false;
uint8_t l_prevEnabledChtm = 0;
uint8_t l_start_htm_index = 0;
uint8_t l_end_htm_index = 0;
// Calculate OCC/HTM requested space
uint64_t l_nhtmSize = i_procAttrs.iv_nhtmBarSize;
uint64_t l_chtmSize = 0;
for (uint8_t ii = 0; ii < NUM_OF_CHTM_REGIONS; ii++)
{
l_chtmSize += i_procAttrs.iv_chtmBarSizes[ii];
}
uint64_t l_htmOccSize = l_nhtmSize + l_chtmSize +
i_procAttrs.iv_occSandboxSize;
FAPI_INF("Selective Mode %d", i_sysAttrs.iv_selectiveMode);
FAPI_INF("l_nhtmSize %.16lld bytes (%d GB), l_chtmSize %.16lld bytes (%d GB) ",
l_nhtmSize, l_nhtmSize >> 30, l_chtmSize, l_chtmSize >> 30);
FAPI_INF("OccSize %.16lld bytes (%d GB)",
i_procAttrs.iv_occSandboxSize, i_procAttrs.iv_occSandboxSize >> 30);
// No HTM/OCC space requested, exit
if (l_htmOccSize == 0)