-
Notifications
You must be signed in to change notification settings - Fork 97
/
p9_setup_sbe_config.C
495 lines (422 loc) · 21.8 KB
/
p9_setup_sbe_config.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
//------------------------------------------------------------------------------
/// @file p9_setup_sbe_config.C
///
/// @brief proc setup sbe config
//------------------------------------------------------------------------------
// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com>
// *HWP Team : Perv
// *HWP Level : 2
// *HWP Consumed by : FSP
//------------------------------------------------------------------------------
//## auto_generated
#include "p9_setup_sbe_config.H"
#include <p9_perv_scom_addresses.H>
#include <p9_perv_scom_addresses_fld.H>
#include <p9_const_common.H>
enum P9_SETUP_SBE_CONFIG_Private_Constants
{
// Scratch_reg_1
ATTR_EQ_GARD_STARTBIT = 0,
ATTR_EQ_GARD_LENGTH = 6,
ATTR_EC_GARD_STARTBIT = 8,
ATTR_EC_GARD_LENGTH = 24,
// Scratch_reg_2
ATTR_I2C_BUS_DIV_REF_STARTBIT = 0,
ATTR_I2C_BUS_DIV_REF_LENGTH = 16,
ATTR_OPTICS_CONFIG_MODE_OBUS0_BIT = 16,
ATTR_OPTICS_CONFIG_MODE_OBUS1_BIT = 17,
ATTR_OPTICS_CONFIG_MODE_OBUS2_BIT = 18,
ATTR_OPTICS_CONFIG_MODE_OBUS3_BIT = 19,
ATTR_MC_PLL_BUCKET_STARTBIT = 21,
ATTR_MC_PLL_BUCKET_LENGTH = 3,
ATTR_OB0_PLL_BUCKET_STARTBIT = 24,
ATTR_OB0_PLL_BUCKET_LENGTH = 2,
ATTR_OB1_PLL_BUCKET_STARTBIT = 26,
ATTR_OB1_PLL_BUCKET_LENGTH = 2,
ATTR_OB2_PLL_BUCKET_STARTBIT = 28,
ATTR_OB2_PLL_BUCKET_LENGTH = 2,
ATTR_OB3_PLL_BUCKET_STARTBIT = 30,
ATTR_OB3_PLL_BUCKET_LENGTH = 2,
// Scratch_reg_3
ATTR_BOOT_FLAGS_STARTBIT = 0,
ATTR_BOOT_FLAGS_LENGTH = 32,
// Scratch_reg_4
ATTR_BOOT_FREQ_MULT_STARTBIT = 0,
ATTR_BOOT_FREQ_MULT_LENGTH = 16,
ATTR_CP_FILTER_BYPASS_BIT = 16,
ATTR_SS_FILTER_BYPASS_BIT = 17,
ATTR_IO_FILTER_BYPASS_BIT = 18,
ATTR_DPLL_BYPASS_BIT = 19,
ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT = 20,
ATTR_OBUS_RATIO_VALUE_BIT = 21,
ATTR_NEST_PLL_BUCKET_STARTBIT = 29,
ATTR_NEST_PLL_BUCKET_LENGTH = 3,
// Scratch_reg_5
ATTR_PLL_MUX_STARTBIT = 12,
ATTR_PLL_MUX_LENGTH = 20,
ATTR_CC_IPL_BIT = 0,
ATTR_INIT_ALL_CORES_BIT = 1,
ATTR_RISK_LEVEL_BIT = 2,
ATTR_DISABLE_HBBL_VECTORS_BIT = 3,
ATTR_MC_SYNC_MODE_BIT = 4,
ATTR_SLOW_PCI_REF_CLOCK_BIT = 5,
// Scratch_reg_6
ATTR_PROC_EFF_FABRIC_GROUP_ID_STARTBIT = 17,
ATTR_PROC_EFF_FABRIC_GROUP_ID_LENGTH = 3,
ATTR_PROC_EFF_FABRIC_CHIP_ID_STARTBIT = 20,
ATTR_PROC_EFF_FABRIC_CHIP_ID_LENGTH = 3,
ATTR_PUMP_CHIP_IS_GROUP = 23,
ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26,
ATTR_PROC_FABRIC_GROUP_ID_LENGTH = 3,
ATTR_PROC_FABRIC_CHIP_ID_STARTBIT = 29,
ATTR_PROC_FABRIC_CHIP_ID_LENGTH = 3,
};
fapi2::ReturnCode p9_setup_sbe_config(const
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
fapi2::buffer<uint32_t> l_read_scratch_reg = 0;
fapi2::buffer<uint32_t> l_read_scratch8 = 0;
fapi2::buffer<uint8_t> l_read_1 = 0;
fapi2::buffer<uint8_t> l_read_2 = 0;
fapi2::buffer<uint16_t> l_read_4 = 0;
fapi2::buffer<uint32_t> l_read_5 = 0;
fapi2::buffer<uint32_t> l_read_6 = 0;
fapi2::buffer<uint32_t> l_data32_cbs_cs;
fapi2::buffer<uint8_t> l_attr_read;
const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
fapi2::ATTR_OPTICS_CONFIG_MODE_Type l_optics_cfg_mode;
FAPI_INF("p9_setup_sbe_config:: Entering ...");
FAPI_DBG("Read Scratch8 for validity of Scratch register");
//Getting SCRATCH_REGISTER_8 register value
FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_8_FSI,
l_read_scratch8)); //l_read_scratch8 = CFAM.SCRATCH_REGISTER_8
//set_scratch1_reg
{
FAPI_DBG("Read Scratch_reg1");
//Getting SCRATCH_REGISTER_1 register value
FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_1_FSI,
l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_1
FAPI_DBG("Reading ATTR_EQ_GARD, ATTR_EC_GARD");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EQ_GARD, i_target_chip, l_read_1));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5));
l_read_1.extractToRight< 0, ATTR_EQ_GARD_LENGTH >(l_read_2);
l_read_5.extractToRight< 0, ATTR_EC_GARD_LENGTH >(l_read_6);
l_read_scratch_reg.insertFromRight< ATTR_EQ_GARD_STARTBIT, ATTR_EQ_GARD_LENGTH >(l_read_2);
l_read_scratch_reg.insertFromRight< ATTR_EC_GARD_STARTBIT, ATTR_EC_GARD_LENGTH >(l_read_6);
FAPI_DBG("Setting up value of Scratch_reg1");
//Setting SCRATCH_REGISTER_1 register value
//CFAM.SCRATCH_REGISTER_1 = l_read_scratch_reg
FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_1_FSI,
l_read_scratch_reg));
l_read_scratch8.setBit<0>();
}
//set_scratch2_reg
{
uint8_t l_ob0_pll_bucket;
uint8_t l_ob1_pll_bucket;
uint8_t l_ob2_pll_bucket;
uint8_t l_ob3_pll_bucket;
FAPI_DBG("Reading Scratch_reg2");
//Getting SCRATCH_REGISTER_2 register value
FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_2_FSI,
l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_2
FAPI_DBG("Reading ATTR_I2C_BUS_DIV_REF");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4));
l_read_scratch_reg.insertFromRight< ATTR_I2C_BUS_DIV_REF_STARTBIT, ATTR_I2C_BUS_DIV_REF_LENGTH >(l_read_4);
for (auto& targ : i_target_chip.getChildren<fapi2::TARGET_TYPE_OBUS>() )
{
// OBUS
uint32_t l_chipletID = targ.getChipletNumber();
FAPI_DBG("Reading ATTR_OPTICS_CONFIG_MODE");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OPTICS_CONFIG_MODE, targ, l_optics_cfg_mode),
"Error from FAPI_ATTR_GET(ATTR_OPTICS_CONFIG_MODE)");
if (l_chipletID == OB0_CHIPLET_ID)
{
l_read_scratch_reg.writeBit<ATTR_OPTICS_CONFIG_MODE_OBUS0_BIT>(((l_optics_cfg_mode ==
fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_SMP)
|| (l_optics_cfg_mode == fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_CAPI)) ? (1) : (0));
}
if (l_chipletID == OB1_CHIPLET_ID)
{
l_read_scratch_reg.writeBit<ATTR_OPTICS_CONFIG_MODE_OBUS1_BIT>(((l_optics_cfg_mode ==
fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_SMP)
|| (l_optics_cfg_mode == fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_CAPI)) ? (1) : (0));
}
if (l_chipletID == OB2_CHIPLET_ID)
{
l_read_scratch_reg.writeBit<ATTR_OPTICS_CONFIG_MODE_OBUS2_BIT>(((l_optics_cfg_mode ==
fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_SMP)
|| (l_optics_cfg_mode == fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_CAPI)) ? (1) : (0));
}
if (l_chipletID == OB3_CHIPLET_ID)
{
l_read_scratch_reg.writeBit<ATTR_OPTICS_CONFIG_MODE_OBUS3_BIT>(((l_optics_cfg_mode ==
fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_SMP)
|| (l_optics_cfg_mode == fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_CAPI)) ? (1) : (0));
}
}
FAPI_DBG("Reading MC PLL buckets");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_PLL_BUCKET, FAPI_SYSTEM, l_read_1));
l_read_scratch_reg.insertFromRight< ATTR_MC_PLL_BUCKET_STARTBIT, ATTR_MC_PLL_BUCKET_LENGTH >(l_read_1);
FAPI_DBG("Reading OB PLL buckets");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket));
l_read_scratch_reg.insertFromRight<ATTR_OB0_PLL_BUCKET_STARTBIT, ATTR_OB0_PLL_BUCKET_LENGTH>(l_ob0_pll_bucket);
l_read_scratch_reg.insertFromRight<ATTR_OB1_PLL_BUCKET_STARTBIT, ATTR_OB1_PLL_BUCKET_LENGTH>(l_ob1_pll_bucket);
l_read_scratch_reg.insertFromRight<ATTR_OB2_PLL_BUCKET_STARTBIT, ATTR_OB2_PLL_BUCKET_LENGTH>(l_ob2_pll_bucket);
l_read_scratch_reg.insertFromRight<ATTR_OB3_PLL_BUCKET_STARTBIT, ATTR_OB3_PLL_BUCKET_LENGTH>(l_ob3_pll_bucket);
FAPI_DBG("Setting up value of Scratch_reg2");
//Setting SCRATCH_REGISTER_2 register value
//CFAM.SCRATCH_REGISTER_2 = l_read_scratch_reg
FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_2_FSI,
l_read_scratch_reg));
l_read_scratch8.setBit<1>();
}
//set_scratch3_reg
{
FAPI_DBG("Reading Scratch_reg3");
//Getting SCRATCH_REGISTER_3 register value
FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_3_FSI,
l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_3
FAPI_DBG("Reading the BOOT_FLAGS");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FLAGS, FAPI_SYSTEM, l_read_5));
l_read_scratch_reg.insertFromRight< ATTR_BOOT_FLAGS_STARTBIT, ATTR_BOOT_FLAGS_LENGTH >(l_read_5);
FAPI_DBG("Setting up value of Scratch_reg3");
//Setting SCRATCH_REGISTER_3 register value
//CFAM.SCRATCH_REGISTER_3 = l_read_scratch_reg
FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_3_FSI,
l_read_scratch_reg));
l_read_scratch8.setBit<2>();
}
//set_scratch4_reg
{
uint8_t l_cp_filter_bypass;
uint8_t l_ss_filter_bypass;
uint8_t l_io_filter_bypass;
uint8_t l_dpll_bypass;
uint8_t l_nest_mem_x_o_pci_bypass;
uint8_t l_attr_obus_ratio = 0;
FAPI_DBG("Reading Scratch_reg4");
//Getting SCRATCH_REGISTER_4 register value
FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_4_FSI,
l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_4
FAPI_DBG("Reading PLL bypass attributes");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, l_cp_filter_bypass),
"Error from FAPI_ATTR_GET (ATTR_CP_FILTER_BYPASS");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip, l_ss_filter_bypass),
"Error from FAPI_ATTR_GET (ATTR_SS_FILTER_BYPASS");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, l_io_filter_bypass),
"Error from FAPI_ATTR_GET (ATTR_IO_FILTER_BYPASS");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DPLL_BYPASS, i_target_chip, l_dpll_bypass),
"Error from FAPI_ATTR_GET (ATTR_DPLL_BYPASS");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_mem_x_o_pci_bypass),
"Error from FAPI_ATTR_GET (ATTR_NEST_MEM_X_O_PCI_BYPASS");
FAPI_DBG("Reading ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1));
l_read_scratch_reg.insertFromRight< ATTR_BOOT_FREQ_MULT_STARTBIT, ATTR_BOOT_FREQ_MULT_LENGTH >(l_read_4);
l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1 & 0x7);
l_read_scratch_reg.writeBit<ATTR_CP_FILTER_BYPASS_BIT>(l_cp_filter_bypass & 0x1);
l_read_scratch_reg.writeBit<ATTR_SS_FILTER_BYPASS_BIT>(l_ss_filter_bypass & 0x1);
l_read_scratch_reg.writeBit<ATTR_IO_FILTER_BYPASS_BIT>(l_io_filter_bypass & 0x1);
l_read_scratch_reg.writeBit<ATTR_DPLL_BYPASS_BIT>(l_dpll_bypass & 0x1);
l_read_scratch_reg.writeBit<ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT>(l_nest_mem_x_o_pci_bypass & 0x1);
// Setting OBUS ratio
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip,
l_attr_obus_ratio));
l_read_scratch_reg.writeBit<ATTR_OBUS_RATIO_VALUE_BIT>(l_attr_obus_ratio & 0x1);
FAPI_DBG("Setting up value of Scratch_reg4");
//Setting SCRATCH_REGISTER_4 register value
//CFAM.SCRATCH_REGISTER_4 = l_read_scratch_reg
FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_4_FSI,
l_read_scratch_reg));
l_read_scratch8.setBit<3>();
}
//set_scratch5_reg
{
uint8_t l_system_ipl_phase;
uint8_t l_force_all_cores;
uint8_t l_risk_level;
uint8_t l_disable_hbbl_vectors;
uint32_t l_pll_mux;
uint8_t l_mc_sync_mode;
uint8_t l_slow_pci_ref_clock;
FAPI_DBG("Reading Scratch_reg5");
//Getting SCRATCH_REGISTER_5 register value
FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_5_FSI,
l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_5
FAPI_DBG("Reading control flag attributes");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_system_ipl_phase));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, l_force_all_cores));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, l_slow_pci_ref_clock));
// set cache contained flag
if (l_system_ipl_phase == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED)
{
l_read_scratch_reg.setBit<ATTR_CC_IPL_BIT>();
}
else
{
l_read_scratch_reg.clearBit<ATTR_CC_IPL_BIT>();
}
// set all cores flag
if (l_force_all_cores)
{
l_read_scratch_reg.setBit<ATTR_INIT_ALL_CORES_BIT>();
}
else
{
l_read_scratch_reg.clearBit<ATTR_INIT_ALL_CORES_BIT>();
}
// set risk level flag
if (l_risk_level == fapi2::ENUM_ATTR_RISK_LEVEL_TRUE)
{
l_read_scratch_reg.setBit<ATTR_RISK_LEVEL_BIT>();
}
else
{
l_read_scratch_reg.clearBit<ATTR_RISK_LEVEL_BIT>();
}
// set disable of HBBL exception vector flag
if (l_disable_hbbl_vectors == fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE)
{
l_read_scratch_reg.setBit<ATTR_DISABLE_HBBL_VECTORS_BIT>();
}
else
{
l_read_scratch_reg.clearBit<ATTR_DISABLE_HBBL_VECTORS_BIT>();
}
// set MC sync mode
if (l_mc_sync_mode)
{
l_read_scratch_reg.setBit<ATTR_MC_SYNC_MODE_BIT>();
}
else
{
l_read_scratch_reg.clearBit<ATTR_MC_SYNC_MODE_BIT>();
}
// set slow PCI ref clock bit
if (l_slow_pci_ref_clock == fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_SLOW)
{
l_read_scratch_reg.clearBit<ATTR_SLOW_PCI_REF_CLOCK_BIT>();
}
else
{
l_read_scratch_reg.setBit<ATTR_SLOW_PCI_REF_CLOCK_BIT>();
}
FAPI_DBG("Reading PLL mux attributes");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_pll_mux));
// set PLL MUX bits
l_read_scratch_reg.insert<ATTR_PLL_MUX_STARTBIT, ATTR_PLL_MUX_LENGTH, 0>(l_pll_mux);
FAPI_DBG("Setting up value of Scratch_reg5");
//Setting SCRATCH_REGISTER_5 register value
//CFAM.SCRATCH_REGISTER_5 = l_read_scratch_reg
FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_5_FSI,
l_read_scratch_reg));
l_read_scratch8.setBit<4>();
}
//set_scratch6_reg
{
uint8_t l_pump_mode;
FAPI_DBG("Reading Scratch_reg6");
//Getting SCRATCH_REGISTER_6 register value
FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_6_FSI,
l_read_scratch_reg)); //l_read_scratch_reg = CFAM.SCRATCH_REGISTER_6
FAPI_DBG("Reading attribute for Hostboot slave bit");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target_chip,
l_read_1));
if ( l_read_1 )
{
l_read_scratch_reg.clearBit<24>();
}
else
{
l_read_scratch_reg.setBit<24>();
}
FAPI_DBG("Reading PUMP MODE");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE,
fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
l_pump_mode));
if (l_pump_mode == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_GROUP)
{
l_read_scratch_reg.setBit<ATTR_PUMP_CHIP_IS_GROUP>();
}
else
{
l_read_scratch_reg.clearBit<ATTR_PUMP_CHIP_IS_GROUP>();
}
FAPI_DBG("Reading ATTR_PROC_FABRIC_GROUP and CHIP_ID");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target_chip,
l_read_1));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip,
l_read_2));
l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_GROUP_ID_STARTBIT, ATTR_PROC_FABRIC_GROUP_ID_LENGTH >(l_read_1);
l_read_scratch_reg.insertFromRight< ATTR_PROC_FABRIC_CHIP_ID_STARTBIT, ATTR_PROC_FABRIC_CHIP_ID_LENGTH >(l_read_2);
FAPI_DBG("Reading ATTR_PROC_EFF_FABRIC_GROUP and CHIP_ID");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID, i_target_chip,
l_read_1));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target_chip,
l_read_2));
l_read_scratch_reg.insertFromRight< ATTR_PROC_EFF_FABRIC_GROUP_ID_STARTBIT, ATTR_PROC_EFF_FABRIC_GROUP_ID_LENGTH >
(l_read_1);
l_read_scratch_reg.insertFromRight< ATTR_PROC_EFF_FABRIC_CHIP_ID_STARTBIT, ATTR_PROC_EFF_FABRIC_CHIP_ID_LENGTH >
(l_read_2);
FAPI_DBG("Setting up value of Scratch_reg6");
//Setting SCRATCH_REGISTER_6 register value
//CFAM.SCRATCH_REGISTER_6 = l_read_scratch_reg
FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_6_FSI,
l_read_scratch_reg));
l_read_scratch8.setBit<5>();
}
FAPI_DBG("Setting Scratch8 for validity of Scratch register");
//Setting SCRATCH_REGISTER_8 register value
//CFAM.SCRATCH_REGISTER_8 = l_read_scratch8
FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SCRATCH_REGISTER_8_FSI,
l_read_scratch8));
//Reading SECURITY_MODE attribute
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SECURITY_MODE, FAPI_SYSTEM, l_attr_read));
if(l_attr_read.getBit<7>() == 0)
{
FAPI_DBG("Reading CBS Control Status register");
FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_CBS_CS_FSI, l_data32_cbs_cs));
if(!l_data32_cbs_cs.getBit<PERV_CBS_CS_SAMPLED_SMD_PIN>()) //SMD=0 indicate chip is in secure mode
{
FAPI_DBG("Changing SAB bit to unsecure mode");
l_data32_cbs_cs.clearBit<PERV_CBS_CS_SECURE_ACCESS_BIT>();
FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_CBS_CS_FSI, l_data32_cbs_cs));
}
}
FAPI_INF("p9_setup_sbe_config: Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}