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p9n2_obus_scom_addresses_fld.H
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p9n2_obus_scom_addresses_fld.H
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/common/include/p9n2_obus_scom_addresses_fld.H $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file p9_obus_scom_addresses_fld.H
/// @brief Defines constants for scom addresses
///
// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: SOA
// *HWP Level: 1
// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
#ifndef __P9N2_OBUS_SCOM_ADDRESSES_FLD_H
#define __P9N2_OBUS_SCOM_ADDRESSES_FLD_H
#include <stdint.h>
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_RX_INVALID_STATE_OR_PARITY_ERROR = 0 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_TX_INVALID_STATE_OR_PARITY_ERROR = 1 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_GCR_HANG_ERROR = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_UNUSED = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_UNUSED_LEN = 45 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_INTERNAL_SCOM_ERROR = 48
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE
= 49 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_RX_INVALID_STATE_OR_PARITY_ERROR = 0 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_TX_INVALID_STATE_OR_PARITY_ERROR = 1 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_GCR_HANG_ERROR = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_UNUSED = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_UNUSED_LEN = 45 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_SCOMFIR_ERROR = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_C0_S0_P0_E9_IOO0_FIR_REG_SCOMFIR_ERROR_CLONE = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_ACTION0_REG_ACTION0 = 0 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_ACTION0_REG_ACTION0_LEN = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_ACTION1_REG_ACTION1 = 0 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_ACTION1_REG_ACTION1_LEN = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_WOF_REG_WOF = 0 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_FIR_WOF_REG_WOF_LEN = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
= 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
= 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
= 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
= 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
48 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
= 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1 = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_2 = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_3 = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_4 = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_5 = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6 = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7 = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
= 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
= 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
= 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
= 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
48 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
= 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1 = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_2 = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_3 = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_4 = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_5 = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6 = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7 = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
= 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
= 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
= 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
= 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
48 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
= 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN = 5
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN = 8 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1 = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2 = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3 = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4 = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5 = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6 = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7 = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_CFG_LTE_MC_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_FIR_PL_RX_PL_FIR_ERRS_RO_SIGNAL_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1 = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_2 = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_3 = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_4 = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_5 = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6 = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7 = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI = 58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_A = 59 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DATA_OFFSET_DISABLE_B = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A = 61 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN = 61 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN = 2
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET = 62 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET = 63 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SL_1STEP_WO_PULSE_SLOW_SIGNAL = 48 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_BUMP_SR_1STEP_WO_PULSE_SLOW_SIGNAL = 49 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_CLEAR_WO_PULSE_SLOW_SIGNAL
= 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BIST_PIPE_DATA_SHIFT = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS = 52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG = 51 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN = 2 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE = 50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN = 3
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL = 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN = 2
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL_RX_PSAVE_MODE_ACTIVE_RO_SIGNAL =
56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL = 48
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_LEFT_EDGE_B_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_RX_PR_RIGHT_EDGE_B_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_A_IP_RO_SIGNAL = 50
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_B_IP_RO_SIGNAL = 51
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_WOBBLE_EDGE_IP_RO_SIGNAL =
52 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_DONE_RO_SIGNAL = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_DDC_FAILED_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SL_1UI_DONE_RO_SIGNAL
= 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_BUMP_SR_1UI_DONE_RO_SIGNAL
= 57 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL_RX_PR_TRACE_STOPPED_RO_SIGNAL =
58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL = 48
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_LEFT_EDGE_A_RO_SIGNAL_LEN =
6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL = 54
;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_RX_PR_RIGHT_EDGE_A_RO_SIGNAL_LEN
= 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ = 60 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_RO_SIGNAL =
48 ;
static const uint8_t
P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_IN_COARSE_MODE_STICKY_RO_SIGNAL = 49 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL =
50 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL_RX_PR_FW_GRAY_CODED_RO_SIGNAL_LEN
= 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN = 53 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN = 4 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA = 55 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS = 58 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN = 5 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN = 6 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL = 54 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN = 3 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1 = 56 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN = 7 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 = 48 ;
static const uint8_t P9N2_OBUS_C0_S0_P0_E9_IOO0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN = 7 ;