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eff_dimm.C
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eff_dimm.C
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: FSP:HB
#include <math.h>
// fapi2
#include <fapi2.H>
#include <vpd_access.H>
#include <utility>
// mss lib
#include <lib/utils/fake_vpd.H>
#include <lib/mss_vpd_decoder.H>
#include <lib/spd/spd_factory.H>
#include <lib/spd/common/spd_decoder.H>
#include <lib/spd/common/rcw_settings.H>
#include <lib/eff_config/timing.H>
#include <lib/dimm/rank.H>
#include <lib/utils/conversions.H>
#include <lib/utils/find.H>
#include <lib/dimm/eff_dimm.H>
#include <lib/dimm/mrs_load.H>
#include <lib/shared/mss_kind.H>
#include <lib/spd/common/dimm_module_decoder.H>
namespace mss
{
using fapi2::TARGET_TYPE_DIMM;
using fapi2::TARGET_TYPE_MCS;
using fapi2::TARGET_TYPE_MCA;
using fapi2::TARGET_TYPE_MCBIST;
///
/// @brief bit encodings for Frequencies RC08
/// @note valid frequency values for Nimbus systems
/// From DDR4 Register v1.0
/// DA[3] : DA17 Input Buffer and QxA17
/// DA[2] QxPAR disabled
/// DA [1:0] QxC[2:0] (Chip ID)
///
enum rc08_encode
{
CID_START = 6,
CID_LENGTH = 2,
ALL_ENABLE = 0b00,
ONE_ZERO_ENABLE = 0b01,
TWO_ONE_ENABLE = 0b10,
ALL_DISABLE = 0b11,
DA17_START = 4,
DA17_LENGTH = 1,
DA17_QA17_LOCATION = 4,
DA17_QA17_ENABLE = 0b0,
DA17_QA17_DISABLE = 0b1,
QXPAR_LOCATION = 5,
PARITY_ENABLE = 0,
PARITY_DISABLE = 1,
MAX_SLAVE_RANKS = 8,
NUM_SLAVE_RANKS_ENCODED_IN_TWO_BITS = 4,
};
///
/// @brief bit encodings for Frequencies RC0A (RC0A)
/// @note valid frequency values for Nimbus systems
/// From DDR4 Register v1.0
/// More encodings available but they won't be used due to system constrains
///
// TODO: RTC 167542
//Do we need to implement v2.0? It would be easy with the new structure - JLH
enum rc0a_encode : uint8_t
{
DDR4_1866 = 0b001,
DDR4_2133 = 0b010,
DDR4_2400 = 0b011,
DDR4_2666 = 0b100,
};
///
/// @brief bit encodings for RC0D (RC0A here) - DIMM Configuration Control Word RC0D (RC0A here)
/// From DDR4 Register v1.0
///
enum rc0d_encode : uint8_t
{
DIRECT_CS_MODE = 0, ///< Direct DualCS mode: Register uses two DCS_n inputes
LRDIMM = 0,
RDIMM = 1,
};
///
/// @brief bit encodings for RC0E
/// From DDR4 Register v1.0
///
enum rc0e_encode
{
RC0E_PARITY_ENABLE_BIT = 7,
RC0E_PARITY_ENABLE = 1,
RC0E_ALERT_N_ASSERT_BIT = 5,
RC0E_ALERT_N_ASERT_PULSE = 1,
RC0E_ALERT_N_REENABLE_BIT = 4,
RC0E_ALERT_N_REENABLE_TRUE = 1,
};
///
/// @brief bit encodings for RC3x - Fine Granularity RDIMM Operating Speed
/// @note Only limited encodings here, more available
/// From DDR4 Register v1.0
///
enum rc3x_encode : uint8_t
{
MT1860_TO_MT1880 = 0x1F,
MT2120_TO_MT2140 = 0x2C,
MT2380_TO_MT2400 = 0x39,
MT2660_TO_MT2680 = 0x47,
};
///
/// @brief bc03_encode enums for Host Interface DQ Driver Control Word
/// From DDR4 Databuffer 01 rev 1.0 and same for DDR4 DataBuffer 02 rev 0.95
///
enum bc03_encode : uint8_t
{
// Bit position of the BC03 bit to enable/ disable DQ/ DQS drivers
BC03_DQ_DISABLE_POS = 4,
BC03_DQ_DISABLE = 1,
BC03_DQ_ENABLE = 0,
};
///
/// @brief bc09_encode enums Power Saving Settings Control Word
///
//Used for hard coding currently
enum bc09_encode : uint8_t
{
BC09_CKE_POWER_DOWN_DISABLE = 0,
BC09_CKE_POWER_DOWN_ENABLE = 1,
BC09_CKE_POWER_DOWN_ENABLE_POS = 4,
BC09_CKE_POWER_ODT_OFF = 1,
BC09_CKE_POWER_ODT_ON = 0,
};
///
/// @brief encoding for DB01 and DB02 as seen from SPD
///
enum lrdimm_databuffers
{
LRDIMM_DB01 = 0b0000,
LRDIMM_DB02 = 0b0001
};
///
/// @brief encoding for MSS_INVALID_FREQ so we can look up functions based on encoding
///
enum invalid_freq_function_encoding
{
RC0A = 0x0a,
RC3X = 0x30,
BC0A = 0x0a,
};
/////////////////////////
// Non-member function implementations
/////////////////////////
///
/// @brief IBT helper - maps from VPD definition of IBT to the RCD control word bit fields
/// @param[in] i_ibt the IBT from VPD (e.g., 10, 15, ...), stored as 10% of original val (10 in VPD == 100 Ohms)
/// @return the IBT bit field e.g., 00, 01 ... (right aligned)
/// @note Unrecognized IBT values will force an assertion.
///
static uint64_t ibt_helper(const uint8_t i_ibt)
{
switch(i_ibt)
{
// Off
case 0:
return 0b11;
break;
// 100 Ohm
case 10:
return 0b00;
break;
// 150 Ohm
case 15:
return 0b01;
break;
// 300 Ohm
case 30:
return 0b10;
break;
default:
FAPI_ERR("unknown IBT value %d", i_ibt);
fapi2::Assert(false);
};
// Not reached, but 'return' off ...
return 0b11;
}
///
/// @brief factory to make an eff_config DIMM object based on dimm kind (type, gen, and revision number)
/// @param[in] i_pDecoder the spd::decoder for the dimm target
/// @param[out] o_fact_obj a shared pointer of the eff_dimm type
///
fapi2::ReturnCode eff_dimm::eff_dimm_factory ( const std::shared_ptr<spd::decoder>& i_pDecoder,
std::shared_ptr<eff_dimm>& o_fact_obj )
{
uint8_t l_type = 0;
uint8_t l_gen = 0;
uint8_t l_buffer_type = 0;
kind_t l_dimm_kind = DEFAULT_KIND;
fapi2::ReturnCode l_rc;
const auto& l_dimm = i_pDecoder->iv_target;
// Now time to get the three attributes to tell which dimm we're working with.
// Dram_gen and dimm_type are set in the SPD factory and we'll call the SPD decoder to get the reg and buff type
FAPI_TRY( eff_dram_gen(l_dimm, l_gen), "Failed eff_dram_gen() accessor for %s", l_dimm );
FAPI_TRY( eff_dimm_type(l_dimm, l_type), "Failed eff_dimm_type() accessor for %s",
l_dimm );
FAPI_TRY( i_pDecoder->iv_module_decoder->register_and_buffer_type(l_buffer_type),
"Failed decoding register and buffer type from SPD for %s", l_dimm );
l_dimm_kind = mss::dimm_kind(l_type, l_gen);
switch (l_dimm_kind)
{
case KIND_LRDIMM_DDR4:
switch (l_buffer_type)
{
case LRDIMM_DB01:
o_fact_obj = std::make_shared<eff_lrdimm_db01>( i_pDecoder, l_rc );
// Assert that l_rc is good and o_fact_object isn't null
FAPI_ASSERT( ((l_rc == fapi2::FAPI2_RC_SUCCESS) && (o_fact_obj != nullptr)),
fapi2::MSS_ERROR_CREATING_EFF_CONFIG_DIMM_OBJECT().
set_DIMM_TYPE(l_type).
set_DRAM_GEN(l_gen).
set_REG_AND_BUFF_TYPE(l_buffer_type).
set_DIMM_TARGET(l_dimm),
"Failure creating an eff_dimm object for an LRDIMM DB01 for target %s buff_type %d",
mss::c_str(l_dimm),
l_buffer_type);
break;
case LRDIMM_DB02:
o_fact_obj = std::make_shared<eff_lrdimm_db02>( i_pDecoder, l_rc );
// Assert that l_rc is good and o_fact_object isn't null
FAPI_ASSERT( ((l_rc == fapi2::FAPI2_RC_SUCCESS) && (o_fact_obj != nullptr)),
fapi2::MSS_ERROR_CREATING_EFF_CONFIG_DIMM_OBJECT().
set_DIMM_TYPE(l_type).
set_DRAM_GEN(l_gen).
set_REG_AND_BUFF_TYPE(l_buffer_type).
set_DIMM_TARGET(l_dimm),
"Failure creating an eff_dimm object for an LRDIMM DB02 for target %s buff_type %d",
mss::c_str(l_dimm),
l_buffer_type);
break;
default:
FAPI_ASSERT(false,
fapi2::MSS_INVALID_LRDIMM_DB().
set_DATA_BUFFER_GEN(l_buffer_type).
set_DIMM_TARGET(l_dimm),
"Error when creating a LRDIMM dimm object due to invalid databuffer type (%d) for target %s",
l_buffer_type,
mss::c_str(l_dimm));
return fapi2::FAPI2_RC_INVALID_PARAMETER;
}
break;
case KIND_RDIMM_DDR4:
o_fact_obj = std::make_shared<eff_rdimm>( i_pDecoder, l_rc );
// Assert that l_rc is good and o_fact_object isn't null
FAPI_ASSERT( ((l_rc == fapi2::FAPI2_RC_SUCCESS) && (o_fact_obj != nullptr)),
fapi2::MSS_ERROR_CREATING_EFF_CONFIG_DIMM_OBJECT().
set_DIMM_TYPE(l_type).
set_DRAM_GEN(l_gen).
set_REG_AND_BUFF_TYPE(l_buffer_type).
set_DIMM_TARGET(l_dimm),
"Failure creating an eff_dimm object for an RDIMM for target %s register type %d",
mss::c_str(l_dimm),
l_buffer_type);
break;
default:
FAPI_ERR("Wrong kind of DIMM plugged in (not DDR4 LRDIMM or RDIMM for target %s", mss::c_str(l_dimm));
FAPI_ASSERT(false,
fapi2::MSS_UNSUPPORTED_DIMM_KIND().
set_DIMM_KIND(l_dimm_kind).
set_DIMM_TYPE(l_type).
set_DRAM_GEN(l_gen).
set_DIMM_TARGET(l_dimm),
"Invalid dimm target when passed into eff_config: kind %d, type %d, gen %d for target %s",
l_dimm_kind,
l_type,
l_gen,
mss::c_str(l_dimm));
}
fapi_try_exit:
return fapi2::current_err;
}
/////////////////////////
// Member Method implementation
/////////////////////////
///
/// @brief Determines & sets effective config for eff_dram_mfg_id type from SPD
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dram_mfg_id()
{
uint16_t l_decoder_val = 0;
uint16_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( eff_dram_mfg_id(iv_mcs, &l_mcs_attrs[0][0]), "Failed accessing ATTR_MSS_EFF_DRAM_MFG_ID" );
FAPI_TRY( iv_pDecoder->dram_manufacturer_id_code(l_decoder_val), "Failed getting dram id code from SPD %s",
mss::c_str(iv_dimm) );
l_mcs_attrs[iv_port_index][iv_dimm_index] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_MFG_ID, iv_mcs, l_mcs_attrs), "Failed to set ATTR_EFF_DRAM_MFG_ID" );
fapi_try_exit:
return fapi2::current_err;
}// dimm_type
///
/// @brief Determines & sets effective config for dram width
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dram_width()
{
uint8_t l_decoder_val = 0;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( iv_pDecoder->device_width(l_decoder_val), "Failed accessing device width from SPD %s", mss::c_str(iv_dimm) );
FAPI_TRY( eff_dram_width(iv_mcs, &l_mcs_attrs[0][0]), "Failed getting EFF_DRAM_WIDTH" );
// Enforcing NIMBUS restrictions
FAPI_ASSERT( (l_decoder_val == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8) ||
(l_decoder_val == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4),
fapi2::MSS_INVALID_DRAM_WIDTH()
.set_DRAM_WIDTH(l_decoder_val)
.set_TARGET(iv_dimm),
"Unsupported DRAM width with %d for target %s",
l_decoder_val,
mss::c_str(iv_dimm));
l_mcs_attrs[iv_port_index][iv_dimm_index] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_WIDTH, iv_mcs, l_mcs_attrs), "Failed setting ATTR_EFF_DRAM_WIDTH" );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for dram density
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dram_density()
{
uint8_t l_decoder_val = 0;
FAPI_TRY( iv_pDecoder->sdram_density(l_decoder_val), "Failed to get dram_density from SPD %s", mss::c_str(iv_dimm) );
// Get & update MCS attribute
{
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dram_density(iv_mcs, &l_mcs_attrs[0][0]), "Failed to get ATTR_MSS_EFF_DRAM_DENSITY" );
l_mcs_attrs[iv_port_index][iv_dimm_index] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_DENSITY, iv_mcs, l_mcs_attrs), "Failed to set ATTR_EFF_DRAM_DENSITY" );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for number of ranks per dimm
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::ranks_per_dimm()
{
uint8_t l_ranks_per_dimm = 0;
uint8_t l_attrs_ranks_per_dimm[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( eff_num_ranks_per_dimm(iv_mcs, &l_attrs_ranks_per_dimm[0][0]), "Failed to get EFF_NUM_RANKS_PER_DIMM" );
FAPI_TRY( iv_pDecoder->logical_ranks_per_dimm(l_ranks_per_dimm),
"Failed to get logical_ranks_per_dimm from SPD %s", mss::c_str(iv_dimm) );
l_attrs_ranks_per_dimm[iv_port_index][iv_dimm_index] = l_ranks_per_dimm;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_NUM_RANKS_PER_DIMM, iv_mcs, l_attrs_ranks_per_dimm),
"Failed to set ATTR_EFF_NUM_RANKS_PER_DIMM" );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for the die count for the DIMM
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::prim_die_count()
{
uint8_t l_die_count = 0;
uint8_t l_attr[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( eff_prim_die_count(iv_mcs, &l_attr[0][0]), "Failed to get EFF_PRIM_DIE_COUNT" );
FAPI_TRY( iv_pDecoder->prim_sdram_die_count(l_die_count),
"Failed to get the die count for the dimm %s", mss::c_str(iv_dimm) );
l_attr[iv_port_index][iv_dimm_index] = l_die_count;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_PRIM_DIE_COUNT, iv_mcs, l_attr),
"Failed to set ATTR_EFF_PRIM_DIE_COUNT" );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for stack type
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::primary_stack_type()
{
uint8_t l_stack_type = 0;
uint8_t l_package_type = 0;
FAPI_TRY( iv_pDecoder->prim_sdram_signal_loading(l_stack_type),
"Failed to get dram_signal_loading from SPD %s", mss::c_str(iv_dimm) );
FAPI_TRY( iv_pDecoder->prim_sdram_package_type(l_package_type),
"Failed to get prim_sdram_package_type from SPD %s", mss::c_str(iv_dimm) );
// Check to see if monolithic DRAM/ SDP
switch (l_package_type)
{
case mss::spd::MONOLITHIC:
// JEDEC standard says if the SPD says monolithic in A[7],
// stack type must be 00 or "SDP" which is what our enum is set to
FAPI_ASSERT( (l_stack_type == fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_SDP),
fapi2::MSS_BAD_SPD()
.set_VALUE(l_stack_type)
.set_BYTE(6)
.set_DIMM_TARGET(iv_dimm),
"Invalid SPD for calculating ATTR_EFF_PRIM_STACK_TYPE");
break;
case mss::spd::NON_MONOLITHIC:
FAPI_ASSERT( (l_stack_type == fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_DDP_QDP) ||
(l_stack_type == fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_3DS),
fapi2::MSS_BAD_SPD()
.set_VALUE(l_stack_type)
.set_BYTE(6)
.set_DIMM_TARGET(iv_dimm),
"Invalid SPD for calculating ATTR_EFF_PRIM_STACK_TYPE");
break;
default:
// SPD decoder should limit this two just two types, if we get here, there was a coding error
FAPI_ERR("Error decoding prim_sdram_package_type");
fapi2::Assert(false);
};
// Get & update MCS attribute
{
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_prim_stack_type(iv_mcs, &l_mcs_attrs[0][0]), "Failed to get ATTR_MSS_EFF_PRIM_STACK_TYPE" );
l_mcs_attrs[iv_port_index][iv_dimm_index] = l_stack_type;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_PRIM_STACK_TYPE, iv_mcs, l_mcs_attrs), "Failed to set EFF_PRIM_STACK_TYPE" );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for dimm size
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dimm_size()
{
std::vector<uint32_t> l_dimm_sizes = { fapi2::ENUM_ATTR_EFF_DIMM_SIZE_4GB,
fapi2::ENUM_ATTR_EFF_DIMM_SIZE_8GB,
fapi2::ENUM_ATTR_EFF_DIMM_SIZE_16GB,
fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB,
fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB,
fapi2::ENUM_ATTR_EFF_DIMM_SIZE_128GB,
fapi2::ENUM_ATTR_EFF_DIMM_SIZE_256GB,
fapi2::ENUM_ATTR_EFF_DIMM_SIZE_512GB,
};
// Retrieve values needed to calculate dimm size
uint8_t l_bus_width = 0;
uint8_t l_sdram_width = 0;
uint8_t l_sdram_density = 0;
uint8_t l_logical_rank_per_dimm = 0;
FAPI_TRY( iv_pDecoder->device_width(l_sdram_width), "Failed to get device width from SPD %s", mss::c_str(iv_dimm) );
FAPI_TRY( iv_pDecoder->prim_bus_width(l_bus_width), "Failed to get prim bus width from SPD %s", mss::c_str(iv_dimm) );
FAPI_TRY( iv_pDecoder->sdram_density(l_sdram_density), "Failed to get dram density from SPD %s", mss::c_str(iv_dimm) );
FAPI_TRY( iv_pDecoder->logical_ranks_per_dimm(l_logical_rank_per_dimm),
"Failed to get logical ranks from SPD %s", mss::c_str(iv_dimm) );
// Let's sort the dimm size vector just to be super duper safe
std::sort( l_dimm_sizes.begin(), l_dimm_sizes.end() );
{
// Double checking to avoid divide by zero errors
// If this fails, there was a problem with the check in SPD function
FAPI_ASSERT( l_sdram_density != 0,
fapi2::MSS_BAD_SDRAM_DENSITY_DECODER()
.set_DRAM_DENSITY(l_sdram_density)
.set_TARGET(iv_dimm),
"SPD decoder messed up and returned a 0. Should have been caught already %s",
mss::c_str(iv_dimm));
// Calculate dimm size
// Formula from SPD Spec (seriously, they don't have parenthesis in the spec)
// Total = SDRAM Capacity / 8 * Primary Bus Width / SDRAM Width * Logical Ranks per DIMM
const uint32_t l_dimm_size = (l_sdram_density * l_bus_width * l_logical_rank_per_dimm) / (8 * l_sdram_width);
FAPI_ASSERT( (std::binary_search(l_dimm_sizes.begin(), l_dimm_sizes.end(), l_dimm_size) == true),
fapi2::MSS_INVALID_CALCULATED_DIMM_SIZE()
.set_SDRAM_WIDTH(l_sdram_width)
.set_BUS_WIDTH(l_bus_width)
.set_DRAM_DENSITY(l_sdram_density)
.set_LOGICAL_RANKS(l_logical_rank_per_dimm)
.set_TARGET(iv_dimm),
"Recieved an invalid dimm size (%d) for calculated DIMM_SIZE for target %s"
"(l_sdram_density %d * l_bus_width %d * l_logical_rank_per_dimm %d) / (8 * l_sdram_width %d",
l_dimm_size,
mss::c_str(iv_dimm),
l_sdram_width,
l_bus_width,
l_sdram_density,
l_logical_rank_per_dimm);
// Get & update MCS attribute
uint32_t l_attrs_dimm_size[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dimm_size(iv_mcs, &l_attrs_dimm_size[0][0]), "Failed to get ATTR_MSS_EFF_DIMM_SIZE" );
l_attrs_dimm_size[iv_port_index][iv_dimm_index] = l_dimm_size;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_SIZE, iv_mcs, l_attrs_dimm_size), "Failed to get ATTR_MSS_EFF_DIMM_SIZE" );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for Hybrid memory type from SPD
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::hybrid_memory_type()
{
uint8_t l_decoder_val = 0;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( eff_hybrid_memory_type(iv_mcs, &l_mcs_attrs[0][0]), "Failed to get ATTR_MSS_HYBRID_MEMORY_TYPE" );
FAPI_TRY(iv_pDecoder->hybrid_media(l_decoder_val), "Failed to get Hybrid_media from SPD %s", mss::c_str(iv_dimm));
l_mcs_attrs[iv_port_index][iv_dimm_index] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE, iv_mcs, l_mcs_attrs),
"Failed to set ATTR_EFF_HYBRID_MEMORY_TYPE" );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for refresh interval time (tREFI)
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dram_trefi()
{
uint64_t l_trefi_in_ps = 0;
// Calculates appropriate tREFI based on fine refresh mode
switch(iv_refresh_mode)
{
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_NORMAL:
FAPI_TRY( calc_trefi( mss::refresh_rate::REF1X,
iv_temp_refresh_range,
l_trefi_in_ps),
"Failed to calculate tREF1 for target %s", mss::c_str(iv_dimm) );
break;
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_2X:
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_2X:
FAPI_TRY( calc_trefi( mss::refresh_rate::REF2X,
iv_temp_refresh_range,
l_trefi_in_ps),
"Failed to calculate tREF2 for target %s", mss::c_str(iv_dimm) );
break;
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_4X:
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_4X:
FAPI_TRY( calc_trefi( mss::refresh_rate::REF4X,
iv_temp_refresh_range,
l_trefi_in_ps),
"Failed to calculate tREF4 for target %s", mss::c_str(iv_dimm) );
break;
default:
// Fine Refresh Mode will be a platform attribute set by the MRW,
// which they "shouldn't" mess up as long as use "attribute" enums.
// if openpower messes this up we can at least catch it
FAPI_ASSERT(false,
fapi2::MSS_INVALID_FINE_REFRESH_MODE().
set_FINE_REF_MODE(iv_refresh_mode),
"%s Incorrect Fine Refresh Mode received: %d ",
mss::c_str(iv_dimm),
iv_refresh_mode);
break;
};
{
// Calculate refresh cycle time in nCK & set attribute
std::vector<uint16_t> l_mcs_attrs_trefi(PORTS_PER_MCS, 0);
uint64_t l_trefi_in_nck = 0;
// Retrieve MCS attribute data
FAPI_TRY( eff_dram_trefi(iv_mcs, l_mcs_attrs_trefi.data()) );
// Calculate nck
FAPI_TRY( spd::calc_nck( l_trefi_in_ps,
static_cast<uint64_t>(iv_tCK_in_ps),
INVERSE_DDR4_CORRECTION_FACTOR,
l_trefi_in_nck),
"Error in calculating tREFI for target %s, with value of l_trefi_in_ps: %d", mss::c_str(iv_dimm), l_trefi_in_ps);
FAPI_INF("tCK (ps): %d, tREFI (ps): %d, tREFI (nck): %d",
iv_tCK_in_ps, l_trefi_in_ps, l_trefi_in_nck);
// Update MCS attribute
l_mcs_attrs_trefi[iv_port_index] = l_trefi_in_nck;
// casts vector into the type FAPI_ATTR_SET is expecting by deduction
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TREFI,
iv_mcs,
UINT16_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trefi, PORTS_PER_MCS)),
"Failed to set tREFI attribute");
}
fapi_try_exit:
return fapi2::current_err;
}// refresh_interval
///
/// @brief Determines & sets effective config for refresh cycle time (tRFC)
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dram_trfc()
{
int64_t l_trfc_mtb = 0;
int64_t l_trfc_in_ps = 0;
// Selects appropriate tRFC based on fine refresh mode
switch(iv_refresh_mode)
{
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_NORMAL:
FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_1(l_trfc_mtb),
"Failed to decode SPD for tRFC1" );
break;
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_2X:
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_2X:
FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_2(l_trfc_mtb),
"Failed to decode SPD for tRFC2" );
break;
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_4X:
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_4X:
FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_4(l_trfc_mtb),
"Failed to decode SPD for tRFC4" );
break;
default:
// Fine Refresh Mode will be a platform attribute set by the MRW,
// which they "shouldn't" mess up as long as use "attribute" enums.
// if openpower messes this up we can at least catch it
FAPI_ASSERT(false,
fapi2::MSS_INVALID_FINE_REFRESH_MODE().
set_FINE_REF_MODE(iv_refresh_mode),
"%s Incorrect Fine Refresh Mode received: %d ",
mss::c_str(iv_dimm),
iv_refresh_mode);
break;
}// switch
// Calculate trfc (in ps)
{
constexpr int64_t l_trfc_ftb = 0;
FAPI_INF( "medium timebase (ps): %ld, fine timebase (ps): %ld, tRFC (MTB): %ld, tRFC(FTB): %ld",
iv_mtb, iv_ftb, l_trfc_mtb, l_trfc_ftb );
l_trfc_in_ps = spd::calc_timing_from_timebase(l_trfc_mtb, iv_mtb, l_trfc_ftb, iv_ftb);
}
{
// Calculate refresh cycle time in nCK & set attribute
uint16_t l_trfc_in_nck = 0;
std::vector<uint16_t> l_mcs_attrs_trfc(PORTS_PER_MCS, 0);
// Retrieve MCS attribute data
FAPI_TRY( eff_dram_trfc(iv_mcs, l_mcs_attrs_trfc.data()),
"Failed to retrieve tRFC attribute" );
// Calculate nck
FAPI_TRY( spd::calc_nck(l_trfc_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trfc_in_nck),
"Error in calculating l_tRFC for target %s, with value of l_trfc_in_ps: %d", mss::c_str(iv_dimm), l_trfc_in_ps);
FAPI_INF("tCK (ps): %d, tRFC (ps): %d, tRFC (nck): %d",
iv_tCK_in_ps, l_trfc_in_ps, l_trfc_in_nck);
// Update MCS attribute
l_mcs_attrs_trfc[iv_port_index] = l_trfc_in_nck;
// casts vector into the type FAPI_ATTR_SET is expecting by deduction
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRFC,
iv_mcs,
UINT16_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trfc, PORTS_PER_MCS) ),
"Failed to set tRFC attribute" );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for refresh cycle time (different logical ranks - tRFC_DLR)
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dram_trfc_dlr()
{
uint8_t l_density = 0;
uint64_t l_tCK_in_ps = 0;
uint64_t l_trfc_dlr_in_ps = 0;
uint8_t l_trfc_dlr_in_nck = 0;
std::vector<uint8_t> l_mcs_attrs_trfc_dlr(PORTS_PER_MCS, 0);
// Retrieve map params
FAPI_TRY( iv_pDecoder->sdram_density(l_density), "Failed to get sdram density");
FAPI_TRY( mss::mrw_fine_refresh_mode(iv_refresh_mode), "Failed to get MRW attribute for fine refresh mode" );
FAPI_INF("Retrieved SDRAM density: %d, fine refresh mode: %d",
l_density, iv_refresh_mode);
// Calculate refresh cycle time in ps
FAPI_TRY( calc_trfc_dlr(iv_dimm, iv_refresh_mode, l_density, l_trfc_dlr_in_ps), "Failed calc_trfc_dlr()" );
// Calculate clock period (tCK) from selected freq from mss_freq
FAPI_TRY( clock_period(iv_dimm, l_tCK_in_ps), "Failed to calculate clock period (tCK)");
// Calculate refresh cycle time in nck
FAPI_TRY( spd::calc_nck(l_trfc_dlr_in_ps, l_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trfc_dlr_in_nck));
FAPI_INF("tCK (ps): %d, tRFC_DLR (ps): %d, tRFC_DLR (nck): %d",
l_tCK_in_ps, l_trfc_dlr_in_ps, l_trfc_dlr_in_nck);
// Retrieve MCS attribute data
FAPI_TRY( eff_dram_trfc_dlr(iv_mcs, l_mcs_attrs_trfc_dlr.data()), "Failed to retrieve tRFC_DLR attribute" );
// Update MCS attribute
l_mcs_attrs_trfc_dlr[iv_port_index] = l_trfc_dlr_in_nck;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRFC_DLR,
iv_mcs,
UINT8_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trfc_dlr, PORTS_PER_MCS) ),
"Failed to set tRFC_DLR attribute" );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for dimm rcd mirror mode
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::rcd_mirror_mode()
{
// Retrieve MCS attribute data
uint8_t l_mirror_mode = 0;
uint8_t l_attrs_mirror_mode[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dimm_rcd_mirror_mode(iv_mcs, &l_attrs_mirror_mode[0][0]) );
// Update MCS attribute
FAPI_TRY( iv_pDecoder->iv_module_decoder->register_to_dram_addr_mapping(l_mirror_mode) );
l_attrs_mirror_mode[iv_port_index][iv_dimm_index] = l_mirror_mode;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RCD_MIRROR_MODE, iv_mcs, l_attrs_mirror_mode) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for dram bank bits
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dram_bank_bits()
{
uint8_t l_bank_bits = 0;
uint8_t l_attrs_bank_bits[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dram_bank_bits(iv_mcs, &l_attrs_bank_bits[0][0]) );
FAPI_TRY( iv_pDecoder->bank_bits(l_bank_bits) );
l_attrs_bank_bits[iv_port_index][iv_dimm_index] = l_bank_bits;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_BANK_BITS, iv_mcs, l_attrs_bank_bits) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for dram row bits
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dram_row_bits()
{
uint8_t l_row_bits = 0;
uint8_t l_attrs_row_bits[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dram_row_bits(iv_mcs, &l_attrs_row_bits[0][0]) );
FAPI_TRY( iv_pDecoder->row_address_bits(l_row_bits) );
l_attrs_row_bits[iv_port_index][iv_dimm_index] = l_row_bits;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_ROW_BITS, iv_mcs, l_attrs_row_bits) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for tDQS
/// @return fapi2::FAPI2_RC_SUCCESS if okay
/// @note Sets TDQS to off for x4, sets to on for x8
///
fapi2::ReturnCode eff_dimm::dram_dqs_time()
{
uint8_t l_attrs_dqs_time[PORTS_PER_MCS] = {};
uint8_t l_dram_width = 0;
// Get the DRAM width
FAPI_TRY( iv_pDecoder->device_width(l_dram_width) );
// Get & update MCS attribute
FAPI_TRY( eff_dram_tdqs(iv_mcs, &l_attrs_dqs_time[0]) );
FAPI_INF("SDRAM width: %d for target %s", l_dram_width, mss::c_str(iv_dimm));
// Enforcing current NIMBUS standards.
FAPI_ASSERT( (l_dram_width == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8) ||
(l_dram_width == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4),
fapi2::MSS_INVALID_DRAM_WIDTH()
.set_DRAM_WIDTH(l_dram_width)
.set_TARGET(iv_dimm),
"Invalid DRAM width with %d for target %s",
l_dram_width,
mss::c_str(iv_dimm));
// Only possible dram width are x4, x8. If x8, tdqs is available, else not available
l_attrs_dqs_time[iv_port_index] = (l_dram_width == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8) ?
fapi2::ENUM_ATTR_EFF_DRAM_TDQS_ENABLE : fapi2::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TDQS, iv_mcs, l_attrs_dqs_time) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for tCCD_L
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dram_tccd_l()
{
int64_t l_tccd_in_ps = 0;
// Get the tCCD_L timing values
// tCCD_L is speed bin independent and is
// the same for all bins within a speed grade.
// It is safe to read this from SPD because the correct nck
// value will be calulated based on our dimm speed.
{
int64_t l_tccd_mtb = 0;
int64_t l_tccd_ftb = 0;
FAPI_TRY( iv_pDecoder->min_tccd_l(l_tccd_mtb),
"Failed min_tccd_l() for %s", mss::c_str(iv_dimm) );
FAPI_TRY( iv_pDecoder->fine_offset_min_tccd_l(l_tccd_ftb),
"Failed fine_offset_min_tccd_l() for %s", mss::c_str(iv_dimm) );
FAPI_INF("medium timebase (ps): %ld, fine timebase (ps): %ld, tCCD_L (MTB): %ld, tCCD_L(FTB): %ld",
iv_mtb, iv_ftb, l_tccd_mtb, l_tccd_ftb );
l_tccd_in_ps = spd::calc_timing_from_timebase(l_tccd_mtb, iv_mtb, l_tccd_ftb, iv_ftb);
}
{
// Calculate refresh cycle time in nCK & set attribute
uint8_t l_tccd_in_nck = 0;
std::vector<uint8_t> l_mcs_attrs_tccd(PORTS_PER_MCS, 0);
// Retrieve MCS attribute data
FAPI_TRY( eff_dram_tccd_l(iv_mcs, l_mcs_attrs_tccd.data()),
"Failed to retrieve tCCD attribute" );
// Calculate nck
FAPI_TRY( spd::calc_nck(l_tccd_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_tccd_in_nck),
"Error in calculating tccd for target %s, with value of l_tccd_in_ps: %d", mss::c_str(iv_dimm), l_tccd_in_ps);
FAPI_INF("tCK (ps): %d, tCCD_L (ps): %d, tCCD_L (nck): %d",
iv_tCK_in_ps, l_tccd_in_ps, l_tccd_in_nck);
// Update MCS attribute
l_mcs_attrs_tccd[iv_port_index] = l_tccd_in_nck;
// casts vector into the type FAPI_ATTR_SET is expecting by deduction
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TCCD_L,
iv_mcs,
UINT8_VECTOR_TO_1D_ARRAY(l_mcs_attrs_tccd, PORTS_PER_MCS) ),
"Failed to set tCCD_L attribute" );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for DIMM RC00
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_dimm::dimm_rc00()
{
// Retrieve MCS attribute data
uint8_t l_attrs_dimm_rc00[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dimm_ddr4_rc00(iv_mcs, &l_attrs_dimm_rc00[0][0]) );
// Update MCS attribute
l_attrs_dimm_rc00[iv_port_index][iv_dimm_index] = iv_pDecoder->iv_raw_card.iv_rc00;
FAPI_INF("%s: RC00 settting: %d", mss::c_str(iv_dimm), l_attrs_dimm_rc00[iv_port_index][iv_dimm_index] );
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_RC00, iv_mcs, l_attrs_dimm_rc00) );
fapi_try_exit: