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p9_start_cbs_errors.xml
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p9_start_cbs_errors.xml
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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/error_info/p9_start_cbs_errors.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2017 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- This is an automatically generated file. -->
<!-- File: p9_start_cbs_errors.xml. -->
<!-- Halt codes for p9_start_cbs -->
<hwpErrors>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_CBS_NOT_IN_IDLE_STATE</rc>
<description>CBS did not complete (did not arrive in IDLE state) within timeout</description>
<collectFfdc>p9_pib2pcb_mux_seq, MASTER_CHIP_TARGET</collectFfdc>
<collectRegisterFfdc>
<id>ROOT_CTRL_REGISTERS_CFAM</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>PERV_CTRL_REGISTERS_CFAM</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>FSI2PIB_STATUS</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>CBS_STATUS_REGISTERS</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<ffdc>CBS_CS_READ</ffdc>
<ffdc>CBS_CS_IDLE_VALUE</ffdc>
<ffdc>LOOP_COUNT</ffdc>
<ffdc>HW_DELAY</ffdc>
<callout>
<target>MASTER_CHIP</target>
<priority>HIGH</priority>
</callout>
<deconfigure>
<target>MASTER_CHIP</target>
</deconfigure>
<gard>
<target>MASTER_CHIP</target>
</gard>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_VDN_PGOOD_NOT_SET</rc>
<description>Nest power (VDN) Power Good indication not set</description>
<collectFfdc>p9_pib2pcb_mux_seq, MASTER_CHIP</collectFfdc>
<collectRegisterFfdc>
<id>ROOT_CTRL_REGISTERS_CFAM</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>PERV_CTRL_REGISTERS_CFAM</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>FSI2PIB_STATUS</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>CBS_STATUS_REGISTERS</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<ffdc>CBS_ENVSTAT_READ</ffdc>
<callout>
<!-- Call out the processor VRM -->
<hw>
<hwid>SPIVID_SLAVE_PART</hwid>
<refTarget>MASTER_CHIP</refTarget>
</hw>
<priority>HIGH</priority>
</callout>
<callout>
<target>MASTER_CHIP</target>
<priority>MEDIUM</priority>
</callout>
<deconfigure>
<target>MASTER_CHIP</target>
</deconfigure>
<gard>
<target>MASTER_CHIP</target>
</gard>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_VDD_NEST_OBSERVE_NOT_SET</rc>
<description>Nest power (VDN) observe bit not set</description>
<collectFfdc>p9_pib2pcb_mux_seq, MASTER_CHIP</collectFfdc>
<collectRegisterFfdc>
<id>ROOT_CTRL_REGISTERS_CFAM</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>PERV_CTRL_REGISTERS_CFAM</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>FSI2PIB_STATUS</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<collectRegisterFfdc>
<id>CBS_STATUS_REGISTERS</id>
<target>MASTER_CHIP</target>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
</collectRegisterFfdc>
<ffdc>FSI2PIB_STATUS_READ</ffdc>
<callout>
<hw>
<!-- Call out the processor VRM -->
<hwid>SPIVID_SLAVE_PART</hwid>
<refTarget>MASTER_CHIP</refTarget>
</hw>
<priority>HIGH</priority>
</callout>
<callout>
<target>MASTER_CHIP</target>
<priority>MEDIUM</priority>
</callout>
<deconfigure>
<target>MASTER_CHIP</target>
</deconfigure>
<gard>
<target>MASTER_CHIP</target>
</gard>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_COLLECT_CC_STATUS_REGISTERS</rc>
<description>Collect clock status registers on cbs fail</description>
<ffdc>UNIT_FFDC_DATA_SL</ffdc>
<ffdc>UNIT_FFDC_DATA_NSL</ffdc>
<ffdc>UNIT_FFDC_DATA_ARY</ffdc>
<ffdc>UNIT_FFDC_DATA_SCAN_REGION</ffdc>
<ffdc>UNIT_FFDC_DATA_CLK_REGION</ffdc>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_OPCG_REGISTERS</rc>
<description>Collect opcg registers on cbs fail</description>
<ffdc>UNIT_FFDC_DATA_OPCG0</ffdc>
<ffdc>UNIT_FFDC_DATA_OPCG1</ffdc>
<ffdc>UNIT_FFDC_DATA_OPCG2</ffdc>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_MUX_SEQ_HW_ERROR</rc>
<description>Collect hw access errors during p9_pib2pcb_mux_seq</description>
<ffdc>UNIT_FFDC_MUX_SEQ_HW_ERROR</ffdc>
</hwpError>
<!-- ******************************************************************** -->
</hwpErrors>