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eff_config.C
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eff_config.C
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file eff_config.C
/// @brief Determine effective config for mss settings
///
// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
// *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: FSP:HB
//utils
#include <math.h>
// fapi2
#include <fapi2.H>
#include <vpd_access.H>
#include <utility>
// mss lib
#include <lib/eff_config/eff_config.H>
#include <lib/utils/fake_vpd.H>
#include <lib/mss_vpd_decoder.H>
#include <lib/spd/spd_factory.H>
#include <lib/spd/common/spd_decoder.H>
#include <lib/spd/common/rcw_settings.H>
#include <lib/eff_config/timing.H>
#include <lib/dimm/rank.H>
#include <lib/utils/conversions.H>
#include <lib/utils/find.H>
using fapi2::TARGET_TYPE_MCA;
using fapi2::TARGET_TYPE_MCS;
using fapi2::TARGET_TYPE_DIMM;
using fapi2::TARGET_TYPE_MCBIST;
namespace mss
{
enum rc10_encode : uint8_t
{
DDR4_1866 = 0x01,
DDR4_2133 = 0x02,
DDR4_2400 = 0x03,
DDR4_2666 = 0x04,
};
enum rc13_encode : uint8_t
{
DIRECT_CS_MODE = 0,
LRDIMM = 0,
RDIMM = 1,
};
enum rc3x_encode : uint8_t
{
MT1860_TO_MT1880 = 0x1F,
MT2120_TO_MT2140 = 0x2C,
MT2380_TO_MT2400 = 0x39,
MT2660_TO_MT2680 = 0x47,
};
/////////////////////////
// Non-member function implementations
/////////////////////////
///
/// @brief IBT helper - maps from VPD definition of IBT to the RCD control word bit fields
/// @param[in] i_ibt the IBT from VPD (e.g., 10, 15, ...)
/// @return the IBT bit field e.g., 00, 01 ... (right aligned)
/// @note Unrecognized IBT values will force an assertion.
///
static uint64_t ibt_helper(const uint8_t i_ibt)
{
switch(i_ibt)
{
// Off
case 0:
return 0b11;
break;
// 100Ohm
case 10:
return 0b00;
break;
// 150Ohm
case 15:
return 0b01;
break;
// 300Ohm
case 30:
return 0b10;
break;
default:
FAPI_ERR("unknown IBT value %d", i_ibt);
fapi2::Assert(false);
};
// Not reached, but 'return' off ...
return 0b11;
}
/////////////////////////
// Member Method implementation
/////////////////////////
///
/// @brief Determines & sets effective config for DRAM generation from SPD
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::dram_gen(const fapi2::Target<TARGET_TYPE_DIMM>& i_target,
const std::vector<uint8_t>& i_spd_data )
{
//TODO: RTC 159777: Change eff_config class to use iv's for mcs, port and dimm position
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_decoder_val = 0;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( eff_dram_gen(l_mcs, &l_mcs_attrs[0][0]) );
FAPI_TRY( spd::dram_device_type(i_target, i_spd_data, l_decoder_val) );
l_mcs_attrs[l_port_num][l_dimm_num] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_GEN, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}// dram_gen
///
/// @brief Determines & sets effective config for DIMM type from SPD
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::dimm_type(const fapi2::Target<TARGET_TYPE_DIMM>& i_target,
const std::vector<uint8_t>& i_spd_data )
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_decoder_val = 0;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( eff_dimm_type(l_mcs, &l_mcs_attrs[0][0]) );
FAPI_TRY( spd::base_module_type(i_target, i_spd_data, l_decoder_val) );
l_mcs_attrs[l_port_num][l_dimm_num] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_TYPE, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}// dimm_type
///
/// @brief Determines & sets effective config for eff_dram_mfg_id type from SPD
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::dram_mfg_id(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint16_t l_decoder_val = 0;
uint16_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( eff_dram_mfg_id(l_mcs, &l_mcs_attrs[0][0]) );
FAPI_TRY( iv_pDecoder->dram_manufacturer_id_code(i_target, l_decoder_val) );
l_mcs_attrs[l_port_num][l_dimm_num] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_MFG_ID, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}// dimm_type
///
/// @brief Determines & sets effective config for dram width
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::dram_width(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_decoder_val = 0;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( iv_pDecoder->device_width(i_target, l_decoder_val) );
FAPI_TRY( eff_dram_width(l_mcs, &l_mcs_attrs[0][0]) );
l_mcs_attrs[l_port_num][l_dimm_num] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_WIDTH, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for the RTT_NOM value
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
/// @note used for MRS01
///
template<>
fapi2::ReturnCode eff_config::dram_rtt_nom<KIND_RDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
//Indexing info
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_decoder_val = 0;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
//Temp holders to grab attributes to then parse into value for this dimm and rank
uint8_t l_rtt_nom[MAX_RANK_PER_DIMM] = {};
//Size per JEDEC spec
constexpr size_t RTT_NOM_SIZE = 8;
// Indexed by denominator. So, if RQZ is 240, and you have OHM240, then you're looking
// for index 1. So this doesn't correspond directly with the table in the JEDEC spec,
// as that's not in "denominator order."
// 0 RQZ/1 RQZ/2 RQZ/3 RQZ/4 RQZ/5 RQZ/6 RQZ/7
constexpr uint8_t rtt_nom_map[] = { 0, 0b100, 0b010, 0b110, 0b001, 0b101, 0b011, 0b111 };
size_t l_rtt_nom_index = 0;
std::vector< uint64_t > l_ranks;
FAPI_TRY( mss::vpd_mt_dram_rtt_nom(i_target, &(l_rtt_nom[0])) );
FAPI_TRY( eff_dram_rtt_nom(l_mcs, &l_mcs_attrs[0][0][0]) );
//Calculate the value for each rank and store in attribute
FAPI_TRY(mss::rank::ranks(i_target, l_ranks));
for (const auto& l_rank : l_ranks)
{
// We have to be careful about 0
l_rtt_nom_index = (l_rtt_nom[mss::index(l_rank)] == 0) ?
0 : fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_NOM_OHM240 / l_rtt_nom[mss::index(l_rank)];
//Make sure it's a valid index
FAPI_ASSERT( (l_rtt_nom_index < RTT_NOM_SIZE),
fapi2::MSS_BAD_MR_PARAMETER()
.set_MR_NUMBER(5)
.set_PARAMETER(RTT_NOM)
.set_PARAMETER_VALUE(l_rtt_nom_index)
.set_DIMM_IN_ERROR(i_target),
"Bad value for RTT NOM: %d (%s)", l_rank, mss::c_str(i_target));
// Map from RTT_NOM array to the value in the map
l_decoder_val = rtt_nom_map[l_rtt_nom_index];
//Store value and move to next rank
l_mcs_attrs[l_port_num][l_dimm_num][mss::index(l_rank)] = l_decoder_val;
}
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_NOM, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for the RTT_NOM value
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
/// @note used for MRS01
///
template<>
fapi2::ReturnCode eff_config::dram_rtt_nom<KIND_LRDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
//Indexing info
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
std::vector< uint64_t > l_ranks;
uint8_t l_decoder_val = 0;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
FAPI_TRY( eff_dram_rtt_nom(l_mcs, &l_mcs_attrs[0][0][0]) );
//Get the value from the LRDIMM SPD
FAPI_TRY( iv_pDecoder->iv_module_decoder->dram_rtt_nom( iv_freq, l_decoder_val));
//Plug into every rank position for the attribute so it'll fit the same style as the RDIMM value
//Same value for every rank for LRDIMMs
FAPI_TRY(mss::rank::ranks(i_target, l_ranks));
for (const auto& l_rank : l_ranks)
{
l_mcs_attrs[l_port_num][l_dimm_num][mss::index(l_rank)] = l_decoder_val;
}
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_NOM, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for the RTT_WR value from SPD
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
/// @note used for MRS02
///
template<>
fapi2::ReturnCode eff_config::dram_rtt_wr<KIND_RDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
std::vector< uint64_t > l_ranks;
uint8_t l_decoder_val = 0;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
FAPI_TRY( eff_dram_rtt_wr(l_mcs, &l_mcs_attrs[0][0][0]) );
//Get RTT_WR from VPD
uint8_t l_dram_rtt_wr[MAX_RANK_PER_DIMM];
FAPI_TRY( mss::vpd_mt_dram_rtt_wr(i_target, &(l_dram_rtt_wr[0])) );
//Calculate the value for each rank and store in attribute
FAPI_TRY(mss::rank::ranks(i_target, l_ranks));
for (const auto& l_rank : l_ranks)
{
const auto l_index = mss::index(l_rank);
switch (l_dram_rtt_wr[l_index])
{
case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_DISABLE:
l_decoder_val = 0b000;
break;
case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_HIGHZ:
l_decoder_val = 0b011;
break;
case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM240:
l_decoder_val = 0b010;
break;
case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM80:
l_decoder_val = 0b100;
break;
case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM120:
l_decoder_val = 0b001;
break;
default:
FAPI_ERR("unknown RTT_WR 0x%x (%s rank %d), dynamic odt off",
l_dram_rtt_wr[l_index], mss::c_str(i_target), l_rank);
l_decoder_val = 0b000;
break;
};
//Store value and move to next rank
l_mcs_attrs[l_port_num][l_dimm_num][mss::index(l_rank)] = l_decoder_val;
}
//Set the attribute
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_WR, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for the RTT_WR value from SPD
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
/// @note used for MRS02
///
template<>
fapi2::ReturnCode eff_config::dram_rtt_wr<KIND_LRDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
std::vector< uint64_t > l_ranks;
uint8_t l_decoder_val = 0;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
//Get the value from the LRDIMM SPD
FAPI_TRY( iv_pDecoder->iv_module_decoder->dram_rtt_wr( iv_freq, l_decoder_val));
//Plug into every rank position for the attribute so it'll fit the same style as the RDIMM value
//Same value for every rank for LRDIMMs
FAPI_TRY(mss::rank::ranks(i_target, l_ranks));
for (const auto& l_rank : l_ranks)
{
l_mcs_attrs[l_port_num][l_dimm_num][mss::index(l_rank)] = l_decoder_val;
}
//Set the attribute
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_WR, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for the RTT_PARK value from SPD
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
/// @note used for MRS05
///
template <>
fapi2::ReturnCode eff_config::dram_rtt_park<KIND_RDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
//Indexing info
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
std::vector< uint64_t > l_ranks;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
// Indexed by denominator. So, if RQZ is 240, and you have OHM240, then you're looking
// for index 1. So this doesn't correspond directly with the table in the JEDEC spec,
// as that's not in "denominator order."
constexpr uint64_t RTT_PARK_COUNT = 8;
// 0 RQZ/1 RQZ/2 RQZ/3 RQZ/4 RQZ/5 RQZ/6 RQZ/7
constexpr uint8_t rtt_park_map[RTT_PARK_COUNT] = { 0, 0b100, 0b010, 0b110, 0b001, 0b101, 0b011, 0b111 };
uint8_t l_rtt_park[MAX_RANK_PER_DIMM];
FAPI_TRY( mss::vpd_mt_dram_rtt_park(i_target, &(l_rtt_park[0])) );
FAPI_TRY( eff_dram_rtt_park(l_mcs, &l_mcs_attrs[0][0][0]) );
//Calculate the value for each rank and store in attribute
FAPI_TRY(mss::rank::ranks(i_target, l_ranks));
for (const auto& l_rank : l_ranks)
{
const auto l_index = mss::index(l_rank);
// We have to be careful about 0
uint8_t l_rtt_park_index = (l_rtt_park[l_index] == 0) ?
0 : fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_PARK_240OHM / l_rtt_park[l_index];
FAPI_ASSERT( (l_rtt_park_index < RTT_PARK_COUNT),
fapi2::MSS_BAD_MR_PARAMETER()
.set_MR_NUMBER(5)
.set_PARAMETER(RTT_PARK)
.set_PARAMETER_VALUE(l_rank)
.set_DIMM_IN_ERROR(i_target),
"Bad value for RTT park: %d (%s)", l_rank, mss::c_str(i_target));
// Map from RTT_PARK array to the value in the map
l_mcs_attrs[l_port_num][l_dimm_num][l_index] = rtt_park_map[l_rtt_park_index];
}
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_PARK, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for the RTT_PARK value from SPD
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
/// @note used for MRS05
///
template <>
fapi2::ReturnCode eff_config::dram_rtt_park<KIND_LRDIMM_DDR4>(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
//Indexing info
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
uint8_t l_decoder_val_01 = 0;
uint8_t l_decoder_val_23 = 0;
FAPI_TRY( eff_dram_rtt_park(l_mcs, &l_mcs_attrs[0][0][0]) );
//Get the value from the LRDIMM SPD
FAPI_TRY( iv_pDecoder->iv_module_decoder->dram_rtt_park_ranks0_1( iv_freq, l_decoder_val_01));;
FAPI_TRY( iv_pDecoder->iv_module_decoder->dram_rtt_park_ranks2_3( iv_freq, l_decoder_val_23));;
l_mcs_attrs[l_port_num][l_dimm_num][0] = l_decoder_val_01;
l_mcs_attrs[l_port_num][l_dimm_num][1] = l_decoder_val_01;
l_mcs_attrs[l_port_num][l_dimm_num][2] = l_decoder_val_23;
l_mcs_attrs[l_port_num][l_dimm_num][3] = l_decoder_val_23;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_PARK, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for dram density
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::dram_density(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
uint8_t l_decoder_val = 0;
FAPI_TRY( iv_pDecoder->sdram_density(i_target, l_decoder_val) );
// Get & update MCS attribute
{
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dram_density(l_mcs, &l_mcs_attrs[0][0]) );
l_mcs_attrs[l_port_num][l_dimm_num] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_DENSITY, l_mcs, l_mcs_attrs) );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for number of ranks per dimm
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::ranks_per_dimm(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_ranks_per_dimm = 0;
uint8_t l_attrs_ranks_per_dimm[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( eff_num_ranks_per_dimm(l_mcs, &l_attrs_ranks_per_dimm[0][0]) );
FAPI_TRY( iv_pDecoder->logical_ranks_per_dimm(i_target, l_ranks_per_dimm) );
l_attrs_ranks_per_dimm[l_port_num][l_dimm_num] = l_ranks_per_dimm;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_NUM_RANKS_PER_DIMM, l_mcs, l_attrs_ranks_per_dimm) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for stack type
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::primary_stack_type(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
uint8_t l_decoder_val = 0;
FAPI_TRY( iv_pDecoder->prim_sdram_signal_loading(i_target, l_decoder_val) );
// Get & update MCS attribute
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_prim_stack_type(l_mcs, &l_mcs_attrs[0][0]) );
l_mcs_attrs[l_port_num][l_dimm_num] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_PRIM_STACK_TYPE, l_mcs, l_mcs_attrs) );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for dimm size
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
/// @warn Dependent on the following attributes already set:
/// @warn eff_dram_density, eff_sdram_width, eff_ranks_per_dimm
///
fapi2::ReturnCode eff_config::dimm_size(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
// Retrieve values needed to calculate dimm size
uint8_t l_bus_width = 0;
uint8_t l_sdram_width = 0;
uint8_t l_sdram_density = 0;
uint8_t l_logical_rank_per_dimm = 0;
FAPI_TRY( iv_pDecoder->device_width(i_target, l_sdram_width) );
FAPI_TRY( iv_pDecoder->prim_bus_width(i_target, l_bus_width) );
FAPI_TRY( iv_pDecoder->sdram_density(i_target, l_sdram_density) );
FAPI_TRY( iv_pDecoder->logical_ranks_per_dimm(i_target, l_logical_rank_per_dimm) );
{
// Calculate dimm size
// Formula from SPD Spec
// Total = SDRAM Capacity 8 * Primary Bus Width SDRAM Width * Logical Ranks per DIMM
uint32_t l_dimm_size = 0;
l_dimm_size = (l_sdram_density / 8.0) * (l_bus_width / l_sdram_width) * l_logical_rank_per_dimm;
// Get & update MCS attribute
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint32_t l_attrs_dimm_size[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dimm_size(l_mcs, &l_attrs_dimm_size[0][0]) );
l_attrs_dimm_size[l_port_num][l_dimm_num] = l_dimm_size;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_SIZE, l_mcs, l_attrs_dimm_size) );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for Hybrid memory type from SPD
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::hybrid_memory_type(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_decoder_val = 0;
uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
// Get & update MCS attribute
FAPI_TRY( eff_hybrid_memory_type(l_mcs, &l_mcs_attrs[0][0]) );
FAPI_TRY(iv_pDecoder->hybrid_media(i_target, l_decoder_val));
l_mcs_attrs[l_port_num][l_dimm_num] = l_decoder_val;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE, l_mcs, l_mcs_attrs) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for refresh interval time (tREFI)
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::dram_trefi(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
uint64_t l_trefi_in_ps = 0;
// Calculates appropriate tREFI based on fine refresh mode
switch(iv_refresh_mode)
{
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_NORMAL:
FAPI_TRY( calc_trefi( mss::refresh_rate::REF1X,
iv_temp_refresh_range,
l_trefi_in_ps),
"Failed to calculate tREF1 for target %s", mss::c_str(i_target) );
break;
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_2X:
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_2X:
FAPI_TRY( calc_trefi( mss::refresh_rate::REF2X,
iv_temp_refresh_range,
l_trefi_in_ps),
"Failed to calculate tREF2 for target %s", mss::c_str(i_target) );
break;
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_4X:
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_4X:
FAPI_TRY( calc_trefi( mss::refresh_rate::REF4X,
iv_temp_refresh_range,
l_trefi_in_ps),
"Failed to calculate tREF4 for target %s", mss::c_str(i_target) );
break;
default:
// Fine Refresh Mode will be a platform attribute set by the MRW,
// which they "shouldn't" mess up as long as use "attribute" enums.
// if openpower messes this up we can at least catch it
FAPI_ASSERT(false,
fapi2::MSS_INVALID_FINE_REFRESH_MODE().
set_FINE_REF_MODE(iv_refresh_mode),
"%s Incorrect Fine Refresh Mode received: %d ",
mss::c_str(i_target),
iv_refresh_mode);
break;
}
{
// Calculate refresh cycle time in nCK & set attribute
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
std::vector<uint16_t> l_mcs_attrs_trefi(PORTS_PER_MCS, 0);
uint64_t l_trefi_in_nck = 0;
// Retrieve MCS attribute data
FAPI_TRY( eff_dram_trefi(l_mcs, l_mcs_attrs_trefi.data()) );
// Calculate nck
FAPI_TRY( spd::calc_nck(l_trefi_in_ps, static_cast<uint64_t>(iv_tCK_in_ps), INVERSE_DDR4_CORRECTION_FACTOR,
l_trefi_in_nck),
"Error in calculating tREFI for target %s, with value of l_trefi_in_ps: %d", mss::c_str(i_target), l_trefi_in_ps);
FAPI_INF("tCK (ps): %d, tREFI (ps): %d, tREFI (nck): %d",
iv_tCK_in_ps, l_trefi_in_ps, l_trefi_in_nck);
// Update MCS attribute
l_mcs_attrs_trefi[l_port_num] = l_trefi_in_nck;
// casts vector into the type FAPI_ATTR_SET is expecting by deduction
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TREFI,
l_mcs,
UINT16_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trefi, PORTS_PER_MCS)),
"Failed to set tREFI attribute");
}
fapi_try_exit:
return fapi2::current_err;
}// refresh_interval
///
/// @brief Determines & sets effective config for refresh cycle time (tRFC)
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::dram_trfc(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
int64_t l_trfc_mtb = 0;
int64_t l_trfc_in_ps = 0;
// Selects appropriate tRFC based on fine refresh mode
switch(iv_refresh_mode)
{
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_NORMAL:
FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_1(i_target, l_trfc_mtb),
"Failed to decode SPD for tRFC1" );
break;
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_2X:
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_2X:
FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_2(i_target, l_trfc_mtb),
"Failed to decode SPD for tRFC2" );
break;
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_4X:
case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_4X:
FAPI_TRY( iv_pDecoder->min_refresh_recovery_delay_time_4(i_target, l_trfc_mtb),
"Failed to decode SPD for tRFC4" );
break;
default:
// Fine Refresh Mode will be a platform attribute set by the MRW,
// which they "shouldn't" mess up as long as use "attribute" enums.
// if openpower messes this up we can at least catch it
FAPI_ASSERT(false,
fapi2::MSS_INVALID_FINE_REFRESH_MODE().
set_FINE_REF_MODE(iv_refresh_mode),
"%s Incorrect Fine Refresh Mode received: %d ",
mss::c_str(i_target),
iv_refresh_mode);
break;
}// switch
// Calculate trfc (in ps)
{
constexpr int64_t l_trfc_ftb = 0;
int64_t l_ftb = 0;
int64_t l_mtb = 0;
FAPI_TRY( iv_pDecoder->medium_timebase(i_target, l_mtb) );
FAPI_TRY( iv_pDecoder->fine_timebase(i_target, l_ftb) );
FAPI_INF( "medium timebase (ps): %ld, fine timebase (ps): %ld, tRFC (MTB): %ld, tRFC(FTB): %ld",
l_mtb, l_ftb, l_trfc_mtb, l_trfc_ftb );
l_trfc_in_ps = spd::calc_timing_from_timebase(l_trfc_mtb, l_mtb, l_trfc_ftb, l_ftb);
}
{
// Calculate refresh cycle time in nCK & set attribute
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
uint16_t l_trfc_in_nck = 0;
std::vector<uint16_t> l_mcs_attrs_trfc(PORTS_PER_MCS, 0);
// Retrieve MCS attribute data
FAPI_TRY( eff_dram_trfc(l_mcs, l_mcs_attrs_trfc.data()),
"Failed to retrieve tRFC attribute" );
// Calculate nck
FAPI_TRY( spd::calc_nck(l_trfc_in_ps, iv_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trfc_in_nck),
"Error in calculating l_tRFC for target %s, with value of l_trfc_in_ps: %d", mss::c_str(i_target), l_trfc_in_ps);
FAPI_INF("tCK (ps): %d, tRFC (ps): %d, tRFC (nck): %d",
iv_tCK_in_ps, l_trfc_in_ps, l_trfc_in_nck);
// Update MCS attribute
l_mcs_attrs_trfc[l_port_num] = l_trfc_in_nck;
// casts vector into the type FAPI_ATTR_SET is expecting by deduction
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRFC,
l_mcs,
UINT16_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trfc, PORTS_PER_MCS) ),
"Failed to set tRFC attribute" );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for refresh cycle time (different logical ranks - tRFC_DLR)
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::dram_trfc_dlr(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
uint8_t l_density = 0;
uint64_t l_tCK_in_ps = 0;
uint64_t l_trfc_dlr_in_ps = 0;
uint8_t l_trfc_dlr_in_nck = 0;
std::vector<uint8_t> l_mcs_attrs_trfc_dlr(PORTS_PER_MCS, 0);
// Retrieve map params
FAPI_TRY( iv_pDecoder->sdram_density(i_target, l_density), "Failed to get sdram density");
FAPI_TRY ( mss::mrw_fine_refresh_mode(iv_refresh_mode), "Failed to get MRW attribute for fine refresh mode" );
FAPI_INF("Retrieved SDRAM density: %d, fine refresh mode: %d",
l_density, iv_refresh_mode);
// Calculate refresh cycle time in ps
FAPI_TRY( calc_trfc_dlr(iv_refresh_mode, l_density, l_trfc_dlr_in_ps), "Failed calc_trfc_dlr()" );
// Calculate clock period (tCK) from selected freq from mss_freq
FAPI_TRY( clock_period(i_target, l_tCK_in_ps), "Failed to calculate clock period (tCK)");
// Calculate refresh cycle time in nck
FAPI_TRY( spd::calc_nck(l_trfc_dlr_in_ps, l_tCK_in_ps, INVERSE_DDR4_CORRECTION_FACTOR, l_trfc_dlr_in_nck));
FAPI_INF("tCK (ps): %d, tRFC_DLR (ps): %d, tRFC_DLR (nck): %d",
l_tCK_in_ps, l_trfc_dlr_in_ps, l_trfc_dlr_in_nck);
// Retrieve MCS attribute data
FAPI_TRY( eff_dram_trfc_dlr(l_mcs, l_mcs_attrs_trfc_dlr.data()), "Failed to retrieve tRFC_DLR attribute" );
// Update MCS attribute
l_mcs_attrs_trfc_dlr[l_port_num] = l_trfc_dlr_in_nck;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_TRFC_DLR,
l_mcs,
UINT8_VECTOR_TO_1D_ARRAY(l_mcs_attrs_trfc_dlr, PORTS_PER_MCS) ),
"Failed to set tRFC_DLR attribute" );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for dimm rcd mirror mode
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::rcd_mirror_mode(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
// Targets
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target);
// Current index
const auto l_port_num = index(l_mca);
const auto l_dimm_num = index(i_target);
// Retrieve MCS attribute data
uint8_t l_mirror_mode = 0;
uint8_t l_attrs_mirror_mode[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dimm_rcd_mirror_mode(l_mcs, &l_attrs_mirror_mode[0][0]) );
// Update MCS attribute
FAPI_TRY( iv_pDecoder->iv_module_decoder->register_to_dram_addr_mapping(l_mirror_mode) );
l_attrs_mirror_mode[l_port_num][l_dimm_num] = l_mirror_mode;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RCD_MIRROR_MODE, l_mcs, l_attrs_mirror_mode) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for dram bank bits
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::dram_bank_bits(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_bank_bits = 0;
uint8_t l_attrs_bank_bits[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dram_bank_bits(l_mcs, &l_attrs_bank_bits[0][0]) );
FAPI_TRY( iv_pDecoder->bank_bits(i_target, l_bank_bits) );
l_attrs_bank_bits[l_port_num][l_dimm_num] = l_bank_bits;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_BANK_BITS, l_mcs, l_attrs_bank_bits) );
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Determines & sets effective config for dram row bits
/// @param[in] i_target FAPI2 target
/// @return fapi2::FAPI2_RC_SUCCESS if okay
///
fapi2::ReturnCode eff_config::dram_row_bits(const fapi2::Target<TARGET_TYPE_DIMM>& i_target)
{
const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target);
const auto l_port_num = index( find_target<TARGET_TYPE_MCA>(i_target) );
const auto l_dimm_num = index(i_target);
uint8_t l_row_bits = 0;
uint8_t l_attrs_row_bits[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
FAPI_TRY( eff_dram_row_bits(l_mcs, &l_attrs_row_bits[0][0]) );
FAPI_TRY( iv_pDecoder->row_address_bits(i_target, l_row_bits) );
l_attrs_row_bits[l_port_num][l_dimm_num] = l_row_bits;
FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_ROW_BITS, l_mcs, l_attrs_row_bits) );
fapi_try_exit:
return fapi2::current_err;
}
///