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dp16.C
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dp16.C
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file dp16.C
/// @brief Static data and subroutines to control the DP16 logic blocks
///
// *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 2
// *HWP Consumed by: FSP:HB
#include <fapi2.H>
#include <utility>
#include <vector>
#include <map>
#include <p9_mc_scom_addresses.H>
#include <p9_mc_scom_addresses_fld.H>
#include <lib/mss_attribute_accessors.H>
#include <lib/phy/dp16.H>
#include <lib/phy/write_cntrl.H>
#include <lib/utils/bit_count.H>
#include <lib/dimm/rank.H>
#include <generic/memory/lib/utils/scom.H>
#include <generic/memory/lib/utils/pos.H>
#include <generic/memory/lib/utils/c_str.H>
#include <lib/workarounds/dp16_workarounds.H>
using fapi2::TARGET_TYPE_MCS;
using fapi2::TARGET_TYPE_MCA;
using fapi2::TARGET_TYPE_DIMM;
using fapi2::TARGET_TYPE_MCBIST;
using fapi2::TARGET_TYPE_SYSTEM;
namespace mss
{
// Definition of the DP16 DLL Config registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DLL_CNFG_REG =
{
MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0,
MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1,
MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2,
MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3,
MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4,
};
// Definition of the DP16 DLL Control registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Control Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_DLL_CNTL0_P0_0, MCA_DDRPHY_DP16_DLL_CNTL1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_CNTL0_P0_1, MCA_DDRPHY_DP16_DLL_CNTL1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_CNTL0_P0_2, MCA_DDRPHY_DP16_DLL_CNTL1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_CNTL0_P0_3, MCA_DDRPHY_DP16_DLL_CNTL1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_CNTL0_P0_4, MCA_DDRPHY_DP16_DLL_CNTL1_P0_4 },
};
// Definition of the DP16 DLL DAC Lower registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_DAC_LOWER_REG =
{
{ MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0, MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1, MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2, MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3, MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4, MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4 },
};
// Definition of the DP16 DLL DAC Upper registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_DAC_UPPER_REG =
{
{ MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0, MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1, MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2, MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3, MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4, MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4 },
};
// Definition of the DP16 DLL Slave Lower registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_SLAVE_LOWER_REG =
{
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4 },
};
// Definition of the DP16 DLL Slave Upper registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_SLAVE_UPPER_REG =
{
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4, MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4 },
};
// Definition of the DP16 DLL SW Control registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_SW_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0, MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1, MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2, MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3, MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4, MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4 },
};
// Definition of the DP16 DLL VREG Coarse registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_VREG_COARSE_REG =
{
{ MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0, MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1, MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2, MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3, MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4, MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4 },
};
// Definition of the DP16 DLL VREG Control registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_VREG_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0, MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1, MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2, MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3, MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4, MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4 },
};
// Definition of the DP16 DLL Extra registers
// DP16 DLL registers all come in pairs - DLL per 8 bits
// 5 DLL per MCA gives us 10 DLL Config Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::DLL_EXTRA_REG =
{
{ MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0, MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0 },
{ MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1, MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1 },
{ MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2, MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2 },
{ MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3, MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3 },
{ MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4, MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4 },
};
// Definition of the DP16 Data Bit Dir1 registers
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DATA_BIT_DIR1_REG
{
MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0,
MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1,
MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2,
MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3,
MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4,
};
// Definition of the DP16 AC Boost Control registers
// DP16 AC Boost registers all come in pairs - one per 8 bits
// 5 DP16 per MCA gives us 10 Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::AC_BOOST_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0 },
{ MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1 },
{ MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2 },
{ MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3 },
{ MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4, MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4 },
};
// Definition of the DP16 CTLE Control registers
// DP16 CTLE Control registers all come in pairs - one per 8 bits
// 5 DP16 per MCA gives us 10 Registers.
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::CTLE_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0, MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0 },
{ MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1, MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1 },
{ MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2, MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2 },
{ MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3, MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3 },
{ MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4, MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4 },
};
// Definition of the IO TX FET slice registers
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::IO_TX_FET_SLICE_REG
{
MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0,
MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1,
MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2,
MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3,
MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4,
};
// Definition of the IO TX PFET slice registers
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::IO_TX_PFET_TERM_REG
{
MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0,
MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1,
MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2,
MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3,
MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4,
};
// Definition of the DP16 RD_VREF Control registers
// DP16 RD_VREF Control registers all come in pairs - one per 8 bits
// 5 DP16 per MCA gives us 10 Registers.
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::RD_VREF_CNTRL_REG =
{
{ MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0 },
{ MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1 },
{ MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2 },
{ MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3 },
{ MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4, MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4 },
};
// Definition of the DP16 RD_VREF Calibration enable registers
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_VREF_CAL_ENABLE_REG =
{
MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0,
MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1,
MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2,
MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3,
MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4,
};
// Definition of the DP16 RD_VREF Calibration enable registers
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_VREF_CAL_ERROR_REG =
{
MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0,
MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1,
MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2,
MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3,
MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4,
};
// Definition of the DP16 Phase Rotator Static Offset registers
// All-caps (as opposed to the others) as it's really in the dp16Traits class which is all caps <shrug>)
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::PR_STATIC_OFFSET_REG
{
MCA_DDRPHY_DP16_WRCLK_PR_P0_0,
MCA_DDRPHY_DP16_WRCLK_PR_P0_1,
MCA_DDRPHY_DP16_WRCLK_PR_P0_2,
MCA_DDRPHY_DP16_WRCLK_PR_P0_3,
MCA_DDRPHY_DP16_WRCLK_PR_P0_4,
};
//////////////////////////////////////
// Defines all WR VREF registers //
//////////////////////////////////////
// Definition of the WR VREF config0 register
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_CONFIG0_REG =
{
MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0,
MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1,
MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2,
MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3,
MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4,
};
// Definition of the WR VREF config1 register
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_CONFIG1_REG =
{
MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0,
MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1,
MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2,
MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3,
MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4,
};
// Definition of the WR VREF status0 register
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_STATUS0_REG =
{
MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0,
MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1,
MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2,
MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3,
MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4,
};
// Definition of the WR VREF status1 register
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_STATUS1_REG =
{
MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0,
MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1,
MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2,
MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3,
MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4,
};
// Definition of the error mask registers element is DP16 number, first is mask 0 second is mask 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_ERROR_MASK_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0, MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1, MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2, MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3, MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4, MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4 },
};
// Definition of the error registers element is DP16 number, first is error 0 second is error 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_ERROR_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0, MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1, MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2, MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3, MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4, MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4 },
};
// Definition of the VREF value registers for RP0 element is DP16 number, first is value 0 second is value 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_VALUE_RP0_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4 },
};
// Definition of the VREF value registers for RP1 element is DP16 number, first is value 0 second is value 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_VALUE_RP1_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4 },
};
// Definition of the VREF value registers for RP2 element is DP16 number, first is value 0 second is value 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_VALUE_RP2_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4 },
};
// Definition of the VREF value registers for RP3 element is DP16 number, first is value 0 second is value 1
const std::vector< std::pair<uint64_t, uint64_t> > dp16Traits<TARGET_TYPE_MCA>::WR_VREF_VALUE_RP3_REG =
{
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3 },
{ MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4, MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4 },
};
// Definition of the windage value registers per MCA. These are per rank pair, per DP16 and there are 2.
const std::vector<uint64_t> dp16Traits<TARGET_TYPE_MCA>::READ_DELAY_OFFSET_REG =
{
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3,
MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4,
};
// Definition of the DISABLE registers, per dp per rank pair
const std::vector< std::vector<std::pair<uint64_t, uint64_t>> > dp16Traits<TARGET_TYPE_MCA>::BIT_DISABLE_REG =
{
{
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4 },
},
{
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4 },
},
{
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4 },
},
{
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3 },
{ MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4, MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4 },
},
};
// we need these declarations here in order for the linker to see the definitions
constexpr const uint64_t dp16Traits<fapi2::TARGET_TYPE_MCA>::GATE_DELAY_BIT_POS[];
constexpr const uint64_t dp16Traits<fapi2::TARGET_TYPE_MCA>::BLUE_WATERFALL_BIT_POS[];
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DATA_BIT_ENABLE0_REG =
{
MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3,
MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4,
};
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::DATA_BIT_ENABLE1_REG =
{
MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0,
MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1,
MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2,
MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3,
MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4,
};
const std::vector< uint64_t > dp16Traits<TARGET_TYPE_MCA>::RD_DIA_CONFIG5_REG =
{
MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0,
MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1,
MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2,
MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3,
MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4,
};
///
/// @brief Given a RD_VREF value, create a PHY 'standard' bit field for that percentage.
/// @tparam T fapi2 Target Type - derived
/// @tparam TT traits type defaults to dp16Traits<T>
/// @param[in] i_target the fapi2 target of the port
/// @param[in] i_vref the value from the mss_vpd_mt_vref_mc_rd attribute for your target
/// @param[out] o_bitfield value of DAC bitfield for given VREF setting
/// @return FAPI2_RC_SUCCESS iff ok
///
template< fapi2::TargetType T, typename TT = dp16Traits<T> >
fapi2::ReturnCode rd_vref_bitfield_helper( const fapi2::Target<T>& i_target,
const uint32_t i_vref,
uint64_t& o_bitfield )
{
FAPI_INF("rd_vref_bitfield_helper for target %s seeing vref percentage: %d", c_str(i_target), i_vref);
// Zero is a special "no-op" value, which we can get if the VPD attributes aren't
// set up. This can happen for an MCA with no functional DIMM present.
if (i_vref == 0)
{
o_bitfield = 0;
return fapi2::FAPI2_RC_SUCCESS;
}
else if ( (i_vref > TT::MAX_RD_VREF) || (i_vref < TT::MIN_RD_VREF) )
{
// Set up some constexprs to work around linker error when pushing traits values into ffdc
constexpr uint64_t l_max = TT::MAX_RD_VREF;
constexpr uint64_t l_min = TT::MIN_RD_VREF;
FAPI_ASSERT( false,
fapi2::MSS_INVALID_VPD_MT_VREF_MC_RD()
.set_VALUE(i_vref)
.set_VREF_MAX(l_max)
.set_VREF_MIN(l_min)
.set_TARGET(i_target),
"Target %s VPD_MT_VREF_MC_RD percentage out of bounds (%d - %d): %d",
c_str(i_target),
l_max,
l_min,
i_vref );
}
else
{
// Per R. King, VREF equation is:
// Vref = 1.1025 for DAC < 15
// Vref = 1.2 - .0065 * DAC for DAC >= 15
// where DAC is simply the 7-bit field value
// note values multiplied by 10 to make everything an integer
o_bitfield = TT::RD_VREF_DVDD * (100000 - i_vref) / TT::RD_VREF_DAC_STEP;
return fapi2::FAPI2_RC_SUCCESS;
}
fapi_try_exit:
return fapi2::current_err;
}
namespace dp16
{
typedef std::pair< uint64_t, uint64_t > register_data_pair;
typedef std::vector< register_data_pair > register_data_vector;
// Why the tables you ask? Because these bits need to be controlled
// depending on phy, packaging, board swizzling and it's just eaiser
// to see the bits like this than in a more compact algorithmic arrangement.
// Systems without Spare Bytes (or with deconfigured spares)
static const register_data_vector data_bit_enable_no_spare[] =
{
// DHPY01
{
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0, 0xFFFF},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1, 0xFFFF},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2, 0xFFFF},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3, 0xFFFF},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4, 0xFF00},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, 0x0},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1, 0x0},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2, 0x0},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3, 0x0},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4, 0x0},
},
};
// Rank Pair will be added to the register address before writing
static const register_data_vector wrclk_enable_no_spare_x4[] =
{
{
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0x8640},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1, 0x8640},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2, 0x8640},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3, 0x8640},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4, 0x8400},
}
};
static const register_data_vector wrclk_enable_no_spare_x8[] =
{
// Port 0 settings
{
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0x0CC0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1, 0xC0C0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2, 0x0CC0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3, 0x0F00},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4, 0x0C00},
},
// Port 1 settings
{
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0xC0C0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1, 0x0F00},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2, 0x0CC0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3, 0xC300},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4, 0x0C00},
},
// Port 2 settings
{
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0xC300},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1, 0xC0C0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2, 0xC0C0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3, 0x0F00},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4, 0x0C00},
},
// Port 3 settings
{
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0x0F00},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1, 0x0F00},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2, 0xC300},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3, 0xC300},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4, 0xC000},
},
// Port 4 settings
// This is flipped w/the settings from the rosetta stone
// due to the port 4 & 6 view from the PHY
{
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0x0CC0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1, 0xC0C0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2, 0x0F00},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3, 0x0F00},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4, 0xC000},
},
// Port 5 settings
// This is flipped w/the settings from the rosetta stone
// due to the port 5 & 7 view from the PHY
{
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0xC300},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1, 0x0CC0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2, 0x0CC0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3, 0xC300},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4, 0xC000},
},
// Port 6 settings
// This is flipped w/the settings from the rosetta stone
// due to the port 4 & 6 view from the PHY
{
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0x0CC0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1, 0x0CC0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2, 0x0CC0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3, 0xC0C0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4, 0x0C00},
},
// Port 7 settings
// This is flipped w/the settings from the rosetta stone
// due to the port 5 & 7 view from the PHY
{
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0x0CC0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1, 0xC0C0},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2, 0x0F00},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3, 0xC300},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4, 0xC000},
},
};
// Some compile constants to define expected sizes
constexpr size_t CLK_ENABLE_X4_SIZE = 1;
constexpr size_t CLK_ENABLE_X8_SIZE = 8;
// Rank Pair will be added to the register address before writing
static const register_data_vector rdclk_enable_no_spare_x4[] =
{
{
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0x8640},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1, 0x8640},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2, 0x8640},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3, 0x8640},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4, 0x8400},
},
};
static const register_data_vector rdclk_enable_no_spare_x8[] =
{
// Port 0 settings
{
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0x0CC0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1, 0xC0C0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2, 0x0CC0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3, 0x0F00},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4, 0x0C00},
},
// Port 1 settings
{
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0xC0C0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1, 0x0F00},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2, 0x0CC0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3, 0xC300},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4, 0x0C00},
},
// Port 2 settings
{
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0xC300},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1, 0xC0C0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2, 0xC0C0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3, 0x0F00},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4, 0x0C00},
},
// Port 3 settings
{
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0x0F00},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1, 0x0F00},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2, 0xC300},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3, 0xC300},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4, 0xC000},
},
// Port 4 settings
// This is flipped w/the settings from the rosetta stone
// due to the port 4 & 6 view from the PHY
{
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0x0CC0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1, 0xC0C0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2, 0x0F00},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3, 0x0F00},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4, 0xC000},
},
// Port 5 settings
// This is flipped w/the settings from the rosetta stone
// due to the port 5 & 7 view from the PHY
{
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0xC300},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1, 0x0CC0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2, 0x0CC0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3, 0xC300},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4, 0xC000},
},
// Port 6 settings
// This is flipped w/the settings from the rosetta stone
// due to the port 4 & 6 view from the PHY
{
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0x0CC0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1, 0x0CC0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2, 0x0CC0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3, 0xC0C0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4, 0x0C00},
},
// Port 7 settings
// This is flipped w/the settings from the rosetta stone
// due to the port 5 & 7 view from the PHY
{
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0x0CC0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1, 0xC0C0},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2, 0x0F00},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3, 0xC300},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4, 0xC000},
},
};
// Systems With Spare Bytes Enabled
static const register_data_vector data_bit_enable_spare[] =
{
// DHPY01
{
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0, 0xFFFF},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1, 0xFFFF},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2, 0xFFFF},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3, 0xFFFF},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4, 0xFFFF},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0, 0x0},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1, 0x0},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2, 0x0},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3, 0x0},
{MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4, 0x0},
},
};
static const register_data_vector wrclk_enable_spare_x4[] =
{
{
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0, 0x8640},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1, 0x8640},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2, 0x8640},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3, 0x8640},
{MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4, 0x8640},
},
};
static const register_data_vector rdclk_enable_spare_x4[] =
{
{
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0, 0x8640},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1, 0x8640},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2, 0x8640},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3, 0x8640},
{MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4, 0x8640},
},
};
///
/// @brief Reset the data bit enable registers
/// @param[in] i_target a port target
/// @return FAPI2_RC_SUCCES iff ok
///
fapi2::ReturnCode reset_data_bit_enable( const fapi2::Target<TARGET_TYPE_MCA>& i_target )
{
// Determine if we're running with spares or not. Once we know that, we can find the right vector to iterate over.
// Note: Is this ATTR_EFF_DIMM_SPARE? Because that's per DIMM, but this is a port-level statement, right? BRS
// Assume Nimbus for now - no spares ever. BRS
bool l_using_spares = false;
// Since this code is the MCA specialization, we know we never deal with DPHY23 - Nimbus PHY are
// 4 copies of the same PHY. So we can use the DPHY01 data for all position.
auto l_reg_data = l_using_spares ? data_bit_enable_spare[0] : data_bit_enable_no_spare[0];
FAPI_DBG("reg/data vector %d", l_reg_data.size());
for (const auto& rdp : l_reg_data)
{
// This is probably important enough to be seen all the time, not just debug
FAPI_INF( "Setting up DATA_BIT_ENABLE 0x%llx (0x%llx) %s", rdp.first, rdp.second, mss::c_str(i_target) );
FAPI_TRY( mss::putScom(i_target, rdp.first, rdp.second) );
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Helper function to select rdclk/wrclk enable settings
/// @tparam N size of x4 register_data_vectors
/// @tparam M size of x8 register_data_vectors
/// @param[in] i_target a port target
/// @param[in] i_clk_enable_data_x4 array of register_data_vectors
/// @param[in] i_clk_enable_data_x8 array of register_data_vectors
/// @param[out] o_reg_data rdclk settings
/// @return FAPI2_RC_SUCCES iff ok
///
template < size_t N, size_t M >
static fapi2::ReturnCode clock_enable_helper( const fapi2::Target<TARGET_TYPE_MCA>& i_target,
const register_data_vector (&i_clk_enable_data_x4)[N],
const register_data_vector (&i_clk_enable_data_x8)[M],
register_data_vector& o_reg_data )
{
// Compile-time checks to assure we don't seg fault
static_assert( (N == CLK_ENABLE_X4_SIZE) &&
(M == CLK_ENABLE_X8_SIZE),
"Expected register_data_vector size for x4 is 1,"
" register_data_vector size for x8 is 8");
// Retrieving DRAM width accessor to determine our device width
// to set appropriate settings for x8 and x4 cases
uint8_t l_dram_width[mss::MAX_DIMM_PER_PORT] = {};
FAPI_TRY( mss::eff_dram_width(i_target, &l_dram_width[0]) );
// I am iterating over functional DIMMs to skip empty DIMM slots
// I'm looking for the 1st instance of whether to use x4 or x8 settings
// This should be fine since 2 DIMMs w/the same width use the same settings
// and DIMM mixing isn't allowed and would error out due to our plug_rules
// before getting here in eff_config
for( const auto& d : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target) )
{
const auto l_sdram_width = l_dram_width[mss::index(d)];
switch(l_sdram_width)
{
case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8:
// Settings for x8 mappings were created for all 8 ports and DP instances
// under a proc since they vary. So are indexing with mss::pos versus mss::index
o_reg_data = i_clk_enable_data_x8[mss::pos(i_target)];
return fapi2::FAPI2_RC_SUCCESS;
break;
case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4:
// Settings for x4 mapping are the same for all 8 ports and DP instances
// so we only use one setting, only the first index is defined
o_reg_data = i_clk_enable_data_x4[0];
return fapi2::FAPI2_RC_SUCCESS;
break;
default:
FAPI_ASSERT( false,
fapi2::MSS_INVALID_DRAM_WIDTH().
set_DRAM_WIDTH(l_sdram_width).
set_TARGET(d),
"Received in valid DRAM width: x%d for %s. "
"Expected x8 or x4 configuration.",
l_sdram_width, mss::c_str(d) );
break;
}// switch
}// dimm
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Reset the read clock enable registers
/// @param[in] i_target
/// @param[in] i_rank_pairs
/// @return FAPI2_RC_SUCCES iff ok
///
fapi2::ReturnCode reset_read_clock_enable( const fapi2::Target<TARGET_TYPE_MCA>& i_target,
const std::vector< uint64_t >& i_rank_pairs )
{
register_data_vector l_reg_data;
FAPI_TRY( clock_enable_helper(i_target, rdclk_enable_no_spare_x4, rdclk_enable_no_spare_x8, l_reg_data),
"Failed clock_enable_helper() on %s", mss::c_str(i_target) );
for (const auto& rp : i_rank_pairs)
{
for (const auto& rdp : l_reg_data)
{
// Grab the register and add the rank pair in
constexpr size_t RP_ADDR_START = 22;
constexpr size_t RP_ADDR_LEN = 2;
fapi2::buffer<uint64_t> l_address(rdp.first);
l_address.insertFromRight<RP_ADDR_START, RP_ADDR_LEN>(rp);
fapi2::buffer<uint64_t> l_data;
constexpr size_t QUAD_LEN = 16;
l_data.insertFromRight<MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK16, QUAD_LEN>(rdp.second);
FAPI_INF( "Setting up RDCLK RP%d 0x%llx (0x%llx) %s", rp, l_address, l_data, mss::c_str(i_target) );
FAPI_TRY( mss::putScom(i_target, l_address, l_data) );
}
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Resets the write clock enable registers
/// @param[in] i_target
/// @param[in] i_rank_pairs
/// @return FAPI2_RC_SUCCESs iff ok
///
fapi2::ReturnCode reset_write_clock_enable( const fapi2::Target<TARGET_TYPE_MCA>& i_target,
const std::vector< uint64_t >& i_rank_pairs )
{
register_data_vector l_reg_data;
FAPI_TRY( clock_enable_helper(i_target, wrclk_enable_no_spare_x4, wrclk_enable_no_spare_x8, l_reg_data),
"Failed clock_enable_helper() on %s", mss::c_str(i_target) );
for (const auto& rp : i_rank_pairs)
{
for (const auto& rdp : l_reg_data)
{
// Grab the register and add the rank pair in
constexpr size_t RP_ADDR_START = 22;
constexpr size_t RP_ADDR_LEN = 2;
fapi2::buffer<uint64_t> l_address(rdp.first);
l_address.insertFromRight<RP_ADDR_START, RP_ADDR_LEN>(rp);
fapi2::buffer<uint64_t> l_data;
constexpr size_t QUAD_LEN = 16;
l_data.insertFromRight<MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK16, QUAD_LEN>(rdp.second);
FAPI_INF( "Setting up WRCLK RP%d 0x%llx (0x%llx) %s", rp, l_address, l_data, mss::c_str(i_target) );
FAPI_TRY( mss::putScom(i_target, l_address, l_data) );
}
}
fapi_try_exit:
return fapi2::current_err;
}
///
/// @brief Reset the training delay configuration
/// @param[in] i_target the port target
/// @param[in] i_rank_pairs vector of rank pairs
/// @return FAPI2_RC_SUCCES iff ok
///