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p9_hcode_image_build.C
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p9_hcode_image_build.C
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C $ */
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file p9_hcode_image_build.C
/// @brief Implements HWP that builds the Hcode image in HOMER.
///
// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com>
// *HWP FW Owner: Prem S Jha <premjha2@in.ibm.com>
// *HWP Team: PM
// *HWP Level: 2
// *HWP Consumed by: Hostboot: Phyp
// *INDENT-OFF*
//--------------------------------------------------------------------------
// Includes
//--------------------------------------------------------------------------
#include <map>
#include <p9_hcode_image_build.H>
#include "p9_xip_image.h"
#include "p9_hcode_image_defines.H"
#include "p9_pm_hcd_flags.h"
#include "p9_stop_util.H"
#include "p9_scan_ring_util.H"
#include "p9_tor.H"
#include "p9_quad_scom_addresses.H"
#include "p9_stop_api.H"
#include <p9_infrastruct_help.H>
#include <p9_xip_customize.H>
#include <p9_quad_scom_addresses.H>
#include <p9_fbc_utils.H>
#include "p9_pstate_parameter_block.H"
#ifdef __CRONUS_VER
#include <string>
#endif
using namespace stopImageSection;
extern "C"
{
/**
* @brief aligns DATA_SIZE to 8B.
* @param TEMP_LEN temp storage
* @param DATA_SIZE size to be aligned. Aligned size is saved in same variable.
*/
#define ALIGN_DWORD(TEMP_LEN, DATA_SIZE) \
{TEMP_LEN = (DATA_SIZE % RING_ALIGN_BOUNDARY); \
if( TEMP_LEN ) \
{ \
(DATA_SIZE = DATA_SIZE + (RING_ALIGN_BOUNDARY - TEMP_LEN));\
} \
}
/**
* @brief aligns start of scan ring to 8B boundary.
* @param RING_REGION_BASE start location of scan ring region in HOMER.
* @param RING_LOC start of scan ring.
*/
#define ALIGN_RING_LOC(RING_REGION_BASE, RING_LOC) \
{ \
uint8_t tempDiff = \
(uint8_t *) RING_LOC - (uint8_t *) RING_REGION_BASE; \
tempDiff = tempDiff %8; \
if( ( tempDiff > 0 ) && ( tempDiff < 8 )) \
{ RING_LOC = RING_LOC + 8 - tempDiff; \
} \
}
/**
* @brief round of ring size to multiple of 32B
*/
#define ROUND_OFF_32B( ROUND_SIZE) \
{ \
uint32_t tempSize = ROUND_SIZE; \
if( tempSize ) \
{ \
ROUND_SIZE = (( ( tempSize + 31 )/32 ) * 32 ); \
} \
}
namespace p9_hcodeImageBuild
{
/**
* @brief some misc local constants
*/
enum
{
ENABLE_ALL_CORE = 0x000FFFF,
RISK_LEVEL = 0x01,
QUAD_COMMON_RING_INDEX_SIZE = sizeof(QuadCmnRingsList_t),
QUAD_SPEC_RING_INDEX_SIZE = ((sizeof(QuadSpecRingsList_t)) / sizeof(uint16_t)),
QUAD_SPEC_RING_INDEX_LEN = (QUAD_SPEC_RING_INDEX_SIZE * 2 * MAX_QUADS_PER_CHIP),
CORE_COMMON_RING_INDEX_SIZE = sizeof(CoreCmnRingsList_t),
CORE_SPEC_RING_INDEX_SIZE = sizeof(CoreSpecRingList_t),
RING_START_TO_RS4_OFFSET = 8,
TOR_VER_ONE = 1,
TOR_VER_TWO = 2,
QUAD_BIT_POS = 24,
ODD_EVEN_EX_POS = 0x00000400,
SECTN_NAME_MAX_LEN = 20,
SGPE_AUX_FUNC_INERVAL_SHIFT = 24,
CME_SRAM_IMAGE = P9_XIP_SECTIONS + 1,
SGPE_SRAM_IMAGE = P9_XIP_SECTIONS + 2,
PGPE_SRAM_IMAGE = P9_XIP_SECTIONS + 3,
EQ_INEX_INDEX = 3, //Using position of erstwhile eq_mode
EQ_INEX_BUCKET_1 = 0,
EQ_INEX_BUCKET_2 = 1,
EQ_INEX_BUCKET_3 = 2,
EQ_INEX_BUCKET_4 = 3,
L3_EPS_DIVIDER = 1,
L2_EPS_DIVIDER = 1,
};
/**
* @brief struct used to manipulate scan ring in HOMER.
*/
struct RingBufData
{
void* iv_pRingBuffer;
uint32_t iv_ringBufSize;
void* iv_pWorkBuf1;
uint32_t iv_sizeWorkBuf1;
void* iv_pWorkBuf2;
uint32_t iv_sizeWorkBuf2;
RingBufData( void* i_pRingBuf1, const uint32_t i_ringSize,
void* i_pWorkBuf1, const uint32_t i_sizeWorkBuf1,
void* i_pWorkBuf2, const uint32_t i_sizeWorkBuf2 ) :
iv_pRingBuffer( i_pRingBuf1),
iv_ringBufSize(i_ringSize),
iv_pWorkBuf1( i_pWorkBuf1 ),
iv_sizeWorkBuf1( i_sizeWorkBuf1 ),
iv_pWorkBuf2( i_pWorkBuf2 ),
iv_sizeWorkBuf2( i_sizeWorkBuf2 )
{}
RingBufData():
iv_pRingBuffer( NULL ),
iv_ringBufSize( 0 ),
iv_pWorkBuf1( NULL ),
iv_sizeWorkBuf1( 0 ),
iv_pWorkBuf2( NULL ),
iv_sizeWorkBuf2( 0 )
{ }
};
/**
* @brief models a section in HOMER.
*/
struct ImgSec
{
PlatId iv_plat;
uint8_t iv_secId;
char iv_secName[SECTN_NAME_MAX_LEN];
ImgSec( PlatId i_plat, uint8_t i_secId, char* i_secName ):
iv_plat( i_plat ),
iv_secId( i_secId )
{
memset( iv_secName, 0x00, SECTN_NAME_MAX_LEN );
uint8_t secLength = strlen(i_secName);
secLength = ( secLength > SECTN_NAME_MAX_LEN ) ? SECTN_NAME_MAX_LEN : secLength;
memcpy( iv_secName, i_secName, secLength );
}
ImgSec( PlatId i_plat, uint8_t i_secId ):
iv_plat( i_plat ),
iv_secId( i_secId )
{
memset( iv_secName, 0x00, SECTN_NAME_MAX_LEN );
}
ImgSec(): iv_plat (PLAT_SELF), iv_secId (0 )
{
memcpy( iv_secName, "Self Restore", 12 );
}
};
/**
* @brief operator < overloading for ImgSec.
*/
bool operator < ( const ImgSec& i_lhs, const ImgSec& i_rhs )
{
if( i_lhs.iv_plat == i_rhs.iv_plat )
{
return i_lhs.iv_secId < i_rhs.iv_secId;
}
else
{
return i_lhs.iv_plat < i_rhs.iv_plat;
}
}
/**
* @brief operator == overloading for ImgSec.
*/
bool operator == ( const ImgSec& i_lhs, const ImgSec& i_rhs )
{
bool equal = false;
if( i_lhs.iv_plat == i_rhs.iv_plat )
{
if( i_lhs.iv_secId == i_rhs.iv_secId )
{
equal = true;
}
}
return equal;
}
/**
* @brief compares size of a given image's section with maximum allowed size.
*/
class ImgSizeBank
{
public:
ImgSizeBank();
~ImgSizeBank() {};
uint32_t isSizeGood( PlatId i_plat, uint8_t i_sec, uint32_t i_size,
char* i_secName, uint8_t i_bufLength );
uint32_t getImgSectn( PlatId i_plat, uint8_t i_sec, uint32_t& o_secSize,
char* i_secName, uint8_t i_bufLength );
private:
std::map< ImgSec, uint32_t> iv_secSize;
};
/**
* @brief constructor
*/
ImgSizeBank::ImgSizeBank()
{
//A given section can be uniquely identified by platform to which it belongs, section id
//within the platform image. Name too has been added to assist debug in case of a failure.
//To identify a given image section say a bootloader, we are using it's id as defined in
//p9_xip_images.h. Inorder to identify a full SRAM Image, we introduced a new ID
//xxx_SRAM_IMAGE.
iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_SELF, (char*)"Self Restore")] = SELF_RESTORE_CODE_SIZE;
iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_CPMR, (char*)"CPMR Header")] = CPMR_HEADER_SIZE;
iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_QPMR, (char*)"QPMR Header")] = HALF_KB;
iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL1_BL, (char*)"SGPE Boot Copier")] = SGPE_BOOT_COPIER_SIZE;
iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL2_BL, (char*)"SGPE Boot Loader")] = SGPE_BOOT_LOADER_SIZE;
iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_HCODE, (char*)"SGPE Hcode")] = SGPE_IMAGE_SIZE;
iv_secSize[ImgSec(PLAT_SGPE, SGPE_SRAM_IMAGE, (char*)"SGPE SRAM Image")] = SGPE_IMAGE_SIZE;
iv_secSize[ImgSec(PLAT_CME, P9_XIP_SECTION_CME_HCODE, (char*)"CME Hcode")] = CME_SRAM_SIZE;
iv_secSize[ImgSec(PLAT_CME, CME_SRAM_IMAGE, (char*)"CME SRAM Image")] = CME_SRAM_SIZE;
iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_PPMR, (char*)"PPMR Header")] = HALF_KB;
iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL1_BL, (char*)"PGPE Boot Copier")] = PGPE_BOOT_COPIER_SIZE;
iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL2_BL, (char*)"PGPE Boot Loader")] = PGPE_BOOT_LOADER_SIZE;;
iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE, (char*)"PGPE Hcode")] = PGPE_IMAGE_SIZE;
iv_secSize[ImgSec(PLAT_PGPE, PGPE_SRAM_IMAGE, (char*)"PGPE SRAM Image")] = PGPE_IMAGE_SIZE;
}
/**
* @brief verifies actual section size against max size allowed.
* @param i_plat platform associated with image section.
* @param i_sec image section.
* @param i_size actual image section size.
* @param i_pSecName points to a buffer with section name.
* @param i_bufLength length of the buffer.
* @return zero if size within limit else max size allowed.
*/
uint32_t ImgSizeBank::isSizeGood( PlatId i_plat, uint8_t i_sec,
uint32_t i_size, char* i_pSecName,
uint8_t i_bufLength )
{
uint32_t rc = 0;
uint32_t tempSize = 0;
ImgSec key( i_plat, i_sec );
std::map< ImgSec, uint32_t>::iterator it;
do
{
rc = getImgSectn( i_plat, i_sec, tempSize, i_pSecName, i_bufLength );
FAPI_DBG(" Sec: %s Max Size 0x%08X", i_pSecName ? i_pSecName : "--", tempSize );
if( rc )
{
FAPI_ERR( "Image Sectn not found i_plat 0x%08x i_sec 0x%08x",
(uint32_t) i_plat, i_sec );
break;
}
if( i_size > tempSize )
{
rc = tempSize; // returning Max Allowed size as return code
break;
}
}
while(0);
return rc;
}
/**
* @brief returns max size for a given image section
* @param i_plat platform associated with image section.
* @param i_sec image section.
* @param i_size actual image section size.
* @param i_pSecName points to a buffer with section name.
* @param i_bufLength length of the buffer.
* @return zero if section found, error code otherwise.
*/
uint32_t ImgSizeBank::getImgSectn( PlatId i_plat, uint8_t i_sec, uint32_t& o_secSize,
char* i_pSecName, uint8_t i_bufLength )
{
uint32_t rc = -1;
ImgSec key( i_plat, i_sec );
std::map< ImgSec, uint32_t>::iterator it;
o_secSize = 0;
for( it = iv_secSize.begin(); it != iv_secSize.end(); it++ )
{
if( key == it->first )
{
rc = 0;
o_secSize = it->second; //Max Size allowed for section
//Image section found and maximum size info obtained.
if( i_pSecName )
{
//Copying Sectn name to assist debug
memcpy( i_pSecName, it->first.iv_secName, i_bufLength );
}
break;
}
}
return rc;
}
/**
* @brief models an Ex pair.
*/
struct ExpairId
{
uint16_t iv_evenExId;
uint16_t iv_oddExId;
/**
* @brief constructor
*/
ExpairId( uint32_t i_evenExId, uint32_t i_oddExId ):
iv_evenExId( i_evenExId ),
iv_oddExId( i_oddExId )
{ }
/**
* @brief constructor
*/
ExpairId() { };
};
/**
* @brief a map to resolve Ex chiplet Id associated with all six quads in P9.
*/
class ExIdMap
{
public:
ExIdMap();
~ExIdMap() {};
uint32_t getInstanceId( uint32_t i_eqId, uint32_t i_ringOrder );
private:
std::map<uint32_t, ExpairId> iv_idMap;
};
#define ALIGN_DBWORD( OUTSIZE, INSIZE ) \
{ \
OUTSIZE = INSIZE; \
if( 0 != (INSIZE/8) ) \
{ \
OUTSIZE = ((( INSIZE + 7 )/ 8) << 3 ); \
} \
}
/**
* @brief constructor
*/
ExIdMap::ExIdMap()
{
ExpairId exPairIdMap[6] = { { 0x10, 0x11},
{ 0x12, 0x13 },
{ 0x14, 0x15 },
{ 0x16, 0x17 },
{ 0x18, 0x19 },
{ 0x1A, 0x1B }
};
for( uint32_t eqCnt = 0; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ )
{
iv_idMap[CACHE0_CHIPLET_ID + eqCnt] = exPairIdMap[eqCnt];
}
}
//-------------------------------------------------------------------------
/**
* @brief returns ex chiplet ID associated with a scan ring and EQ id.
* @param i_eqId chiplet id for a given quad.
* @param i_ringOrder serial number associated with a scan ring in HOMER.
* @return chiplet Id associated with a scan ring.
*/
uint32_t ExIdMap::getInstanceId( uint32_t i_eqId, uint32_t i_ringOrder )
{
uint32_t exChipletId = 0xFFFFFFFF;
std::map<uint32_t, ExpairId>::iterator itChipId = iv_idMap.find( i_eqId );
do
{
if ( itChipId == iv_idMap.end() )
{
break;
}
else
{
switch( i_ringOrder )
{
case 0:
exChipletId = i_eqId;
break;
case 1:
case 3:
case 5:
case 7:
exChipletId = itChipId->second.iv_evenExId;
break;
case 2:
case 4:
case 6:
case 8:
exChipletId = itChipId->second.iv_oddExId;
break;
default:
break;
}
}
}
while(0);
FAPI_DBG("Resolved Ex Id 0x%02x", exChipletId );
return exChipletId;
}
//-------------------------------------------------------------------------
fapi2::ReturnCode validateSramImageSize( Homerlayout_t* i_pChipHomer, uint32_t& o_sramImgSize )
{
FAPI_DBG(">validateSramImageSize" );
uint32_t rc = IMG_BUILD_SUCCESS;
ImgSizeBank sizebank;
cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
QpmrHeaderLayout_t* pQpmrHdr = ( QpmrHeaderLayout_t*) & (i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader);
PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader;
o_sramImgSize = SWIZZLE_4_BYTE(pQpmrHdr->sgpeSramImageSize);
rc = sizebank.isSizeGood( PLAT_SGPE, SGPE_SRAM_IMAGE, o_sramImgSize, NULL , 0 );
FAPI_IMP("SGPE SRAM Image Size : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" );
FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ),
fapi2::SGPE_IMG_EXCEED_SRAM_SIZE( )
.set_BAD_IMG_SIZE( o_sramImgSize )
.set_MAX_SGPE_IMG_SIZE_ALLOWED( rc ),
"SGPE Image Size Exceeded Max Allowed Size" );
o_sramImgSize = (SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset) << CME_BLK_SIZE_SHIFT) +
SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length);
FAPI_DBG("CME Offset 0x%08X size 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset), o_sramImgSize );
rc = sizebank.isSizeGood( PLAT_CME, CME_SRAM_IMAGE, o_sramImgSize, NULL, 0 );
FAPI_IMP("CME SRAM Image Size : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" );
FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ),
fapi2::CME_IMG_EXCEED_SRAM_SIZE( )
.set_BAD_IMG_SIZE( o_sramImgSize )
.set_MAX_CME_IMG_SIZE_ALLOWED( rc ),
"CME Image Size Exceeded Max Allowed Size" );
o_sramImgSize = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size);
rc = sizebank.isSizeGood( PLAT_PGPE, PGPE_SRAM_IMAGE, o_sramImgSize, NULL, 0 );
FAPI_IMP("PGPE SRAM Image Size : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" );
FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ),
fapi2::PGPE_IMG_EXCEED_SRAM_SIZE( )
.set_BAD_IMG_SIZE( o_sramImgSize )
.set_MAX_PGPE_IMG_SIZE_ALLOWED( rc ),
"PGPE Image Size Exceeded Max Allowed Size" );
FAPI_DBG("<validateSramImageSize" );
fapi_try_exit:
return fapi2::current_err;
}
//-------------------------------------------------------------------------
/**
* @brief validates arguments passed for hcode image build
* @param refer to p9_hcode_image_build arguments
* @return fapi2 return code
*/
fapi2::ReturnCode validateInputArguments( void* const i_pImageIn, void* i_pImageOut,
SysPhase_t i_phase, ImageType_t i_imgType,
void* i_pBuf1, uint32_t i_bufSize1, void* i_pBuf2,
uint32_t i_bufSize2, void* i_pBuf3, uint32_t i_bufSize3 )
{
uint32_t l_rc = IMG_BUILD_SUCCESS;
uint32_t hwImagSize = 0;
FAPI_DBG("Entering validateInputArguments ...");
FAPI_ASSERT( (( i_pImageIn != NULL ) && ( i_pImageOut != NULL ) &&
( i_pImageIn != i_pImageOut )),
fapi2::IMG_PTR_ERROR()
.set_HW_IMG_BUF_PTR( i_pImageIn )
.set_HOMER_IMG_BUF_PTR( i_pImageOut ),
"Bad pointer to HW Image or HOMER Image" );
l_rc = p9_xip_image_size( i_pImageIn, &hwImagSize );
FAPI_DBG("size is 0x%08X; xip_image_size RC is 0x%02x HARDWARE_IMG_SIZE 0x%08X Sz 0x%08X",
hwImagSize, l_rc, HARDWARE_IMG_SIZE, hwImagSize );
FAPI_ASSERT( (( IMG_BUILD_SUCCESS == l_rc ) && ( hwImagSize > 0 ) &&
( HARDWARE_IMG_SIZE >= hwImagSize )),
fapi2::HW_IMAGE_INVALID_SIZE()
.set_HW_IMG_SIZE( hwImagSize )
.set_MAX_HW_IMG_SIZE( HARDWARE_IMG_SIZE ),
"Hardware image size found out of range" );
FAPI_ASSERT( (( i_phase > PHASE_NA ) && ( i_phase < PHASE_END )),
fapi2::HCODE_INVALID_PHASE()
.set_SYS_PHASE( i_phase ),
"Invalid value passed as build phase" );
FAPI_ASSERT( ( i_pBuf1 != NULL ),
fapi2::HCODE_INVALID_TEMP_BUF()
.set_TEMP_BUF_PTR( i_pBuf1 ),
"Invalid temp buffer1 passed for hcode image build" );
FAPI_ASSERT( (( i_bufSize1 != 0 ) && ( i_bufSize2 != 0 ) && ( i_bufSize3 != 0 )),
fapi2::HCODE_TEMP_BUF_SIZE()
.set_TEMP_BUF1_SIZE( i_bufSize1 )
.set_TEMP_BUF2_SIZE( i_bufSize2 )
.set_TEMP_BUF3_SIZE( i_bufSize3 ),
"Invalid work buffer size " );
FAPI_ASSERT( ( i_pBuf2 != NULL ),
fapi2::HCODE_INVALID_TEMP_BUF()
.set_TEMP_BUF_PTR( i_pBuf2 ),
"Invalid temp buffer2 passed for hcode image build" );
FAPI_ASSERT( ( i_pBuf3 != NULL ),
fapi2::HCODE_INVALID_TEMP_BUF()
.set_TEMP_BUF_PTR( i_pBuf3 ),
"Invalid temp buffer3 passed for hcode image build" );
FAPI_ASSERT( ( i_imgType.isBuildValid() ),
fapi2::HCODE_INVALID_IMG_TYPE(),
"Invalid image type passed for hcode image build" );
FAPI_DBG("Exiting validateInputArguments ...");
fapi_try_exit:
return fapi2::current_err;
}
//------------------------------------------------------------------------------
/**
* @brief Copies section of hardware image to HOMER
* @param i_destPtr a location in HOMER
* @param i_srcPtr a location in HW Image.
* @param i_secId XIP Section id to be copied.
* @param i_platId platform associated with the given section.
* @param o_ppeSection contains section details.
* @return IMG_BUILD_SUCCESS if successful, error code otherwise.
*/
uint32_t copySectionToHomer( uint8_t* i_destPtr, uint8_t* i_srcPtr, uint8_t i_secId, PlatId i_platId ,
P9XipSection& o_ppeSection )
{
FAPI_INF("> copySectionToHomer");
uint32_t retCode = IMG_BUILD_SUCCESS;
ImgSizeBank sizebank;
do
{
char secName[SECTN_NAME_MAX_LEN] = {0};
o_ppeSection.iv_offset = 0;
o_ppeSection.iv_size = 0;
uint32_t rcTemp = p9_xip_get_section( i_srcPtr, i_secId, &o_ppeSection );
if( rcTemp )
{
FAPI_ERR("Failed to get section 0x%08X of Plat 0x%08X", i_secId, i_platId );
retCode = BUILD_FAIL_INVALID_SECTN;
break;
}
FAPI_DBG("o_ppeSection.iv_offset = %X, "
"o_ppeSection.iv_size = %X, "
"i_secId %d",
o_ppeSection.iv_offset,
o_ppeSection.iv_size,
i_secId);
rcTemp = sizebank.isSizeGood( i_platId, i_secId, o_ppeSection.iv_size, secName, SECTN_NAME_MAX_LEN );
if ( rcTemp )
{
FAPI_ERR("??????????Size Exceeds the permissible limit???????" );
FAPI_ERR("Sec Name: %s Max Allowed 0x%08X (%08d) Actual Size 0x%08X (%08d)",
secName, rcTemp, rcTemp, o_ppeSection.iv_size, o_ppeSection.iv_size);
retCode = BUILD_SEC_SIZE_OVERFLOW;
break;
}
memcpy( i_destPtr, i_srcPtr + o_ppeSection.iv_offset, o_ppeSection.iv_size );
}
while(0);
FAPI_INF("< copySectionToHomer");
return retCode;
}
//------------------------------------------------------------------------------
/**
* @brief Update the CME/SGPE Image Header Flag field.
* @param i_pChipHomer points to HOMER image.
* @return fapi2 return code.
*/
fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt )
{
uint8_t attrVal = 0;
uint64_t chtmVal = 0;
uint32_t cmeFlag = 0;
uint32_t sgpeFlag = 0;
uint16_t qmFlags = 0;
pgpe_flags_t pgpeFlags;
pgpeFlags.value = 0;
const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE];
PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)& i_pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE];
//Handling flags common to CME and SGPE
FAPI_DBG(" ==================== CME/SGPE Flags =================");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP4_DISABLE,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_STOP4_DISABLE");
if( attrVal )
{
cmeFlag |= CME_STOP_4_TO_2_BIT_POS;
sgpeFlag |= SGPE_STOP_4_TO_2_BIT_POS;
}
FAPI_DBG("STOP_4_to_2 : %s", attrVal ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP5_DISABLE,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_STOP5_DISABLE");
if( attrVal )
{
cmeFlag |= CME_STOP_5_TO_4_BIT_POS;
sgpeFlag |= SGPE_STOP_5_TO_4_BIT_POS;
}
FAPI_DBG("STOP_5_to_4 : %s", attrVal ? "TRUE" : "FALSE");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP8_DISABLE,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_STOP8_DISABLE");
if( attrVal )
{
cmeFlag |= CME_STOP_8_TO_5_BIT_POS;
sgpeFlag |= SGPE_STOP_8_TO_5_BIT_POS;
}
FAPI_DBG("STOP_8_to_5 : %s", attrVal ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP11_DISABLE,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_STOP11_DISABLE");
if( attrVal )
{
cmeFlag |= CME_STOP_11_TO_8_BIT_POS;
sgpeFlag |= SGPE_STOP_11_TO_8_BIT_POS;
}
FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_INSTRUCTION_TRACE_ENABLE,
i_procTgt,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_CME_INSTRUCTION_TRACE_ENABLE");
if( attrVal )
{
sgpeFlag |= SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS;
}
FAPI_DBG("CME Instruction Trace Enabled : %s", attrVal ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_CHTM_TRACE_ENABLE,
i_procTgt,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_CME_CHTM_TRACE_ENABLE");
if( attrVal )
{
sgpeFlag |= SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS;
}
FAPI_DBG("CME CHTM Trace Enabled : %s", attrVal ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_CHTM_TRACE_MEMORY_CONFIG,
i_procTgt,
chtmVal),
"Error from FAPI_ATTR_GET for attribute ATTR_CME_CHTM_TRACE_MEMORY_CONFIG" );
if( chtmVal )
{
pSgpeHdr->g_sgpe_chtm_mem_cfg = SWIZZLE_8_BYTE(chtmVal);
}
FAPI_DBG("CME CHTM Memory Config : %016llx", chtmVal);
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_RESCLK_ENABLE,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_RESCLK_ENABLE" );
if( attrVal )
{
qmFlags |= CME_QM_FLAG_RESCLK_ENABLE;
pgpeFlags.fields.resclk_enable = 1;
}
FAPI_DBG("Resonant Clock Enable : %s", attrVal ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IVRMS_ENABLED,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_IVRMS_ENABLED" );
if( attrVal )
{
qmFlags |= CME_QM_FLAG_SYS_IVRM_ENABLE;
pgpeFlags.fields.ivrm_enable = 1;
}
FAPI_DBG("System IVRM Enable : %s", attrVal ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_VDM_ENABLE" );
if( attrVal )
{
qmFlags |= CME_QM_FLAG_SYS_VDM_ENABLE;
pgpeFlags.fields.vdm_enable = 1;
}
FAPI_DBG("System VDM Enable : %s", attrVal ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_PUMP_MODE_MODE");
//Attribute set to 0x01 for CHIP_IS_NODE, 0x02 for CHIP_IS_GROUP
if( attrVal == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_NODE )
{
sgpeFlag |= SGPE_PROC_FAB_PUMP_MODE_BIT_POS;
}
FAPI_DBG("FAB_PUMP_MODE : %s", (attrVal == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_NODE) ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_WOF_ENABLED,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_WOF_ENABLED" );
if( attrVal )
{
qmFlags |= CME_QM_FLAG_SYS_WOF_ENABLE;
pgpeFlags.fields.wof_enable = 1;
}
FAPI_DBG("System WOF Enable : %s", attrVal ? "TRUE" : "FALSE" );
// Set PGPE Header Flags from Attributes
FAPI_DBG(" -------------------- PGPE Flags -----------------");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PGPE_HCODE_FUNCTION_ENABLE,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_PGPE_HCODE_FUNCTION_ENABLE");
// If 0 (Hcode disabled), then set the occ_opc_immed_response flag bit
if( !attrVal )
{
pgpeFlags.fields.occ_ipc_immed_response = 1;
}
FAPI_DBG("PGPE Hcode Mode : %s", attrVal ? "PSTATES Enabled" : "OCC IPC Immediate Response Mode" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_WOF_ENABLE_FRATIO,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_WOF_ENABLE_FRATIO" );
if( attrVal )
{
pgpeFlags.fields.enable_fratio = 1;
}
FAPI_DBG("System FRATIO ENABLE : %s", attrVal ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_WOF_ENABLE_VRATIO,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_WOF_ENABLE_VRATIO" );
if( attrVal )
{
pgpeFlags.fields.enable_vratio = 1;
}
FAPI_DBG("System VRATIO ENABLE : %s", attrVal ? "TRUE" : "FALSE" );
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_WOF_VRATIO_SELECT,
FAPI_SYSTEM,
attrVal),
"Error from FAPI_ATTR_GET for attribute ATTR_WOF_VRATIO_SELECT" );
if( attrVal )
{
pgpeFlags.fields.vratio_modifier = 1;
}
FAPI_DBG("System VRATIO SELECT: %s", attrVal ? "TRUE" : "FALSE" );
// Updating flag fields in the headers
pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(cmeFlag);
pCmeHdr->g_cme_qm_mode_flags = SWIZZLE_2_BYTE(qmFlags);
pSgpeHdr->g_sgpe_reserve_flags = SWIZZLE_4_BYTE(sgpeFlag);
pPgpeHdr->g_pgpe_flags = SWIZZLE_2_BYTE(pgpeFlags.value);
FAPI_INF("CME Flag Value : 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags));
FAPI_INF("CME QM Flag Value : 0x%08x", SWIZZLE_2_BYTE(pCmeHdr->g_cme_qm_mode_flags));
FAPI_INF("SGPE Flag Value : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags));
FAPI_INF("SGPE Chtm Config : 0x%016llx", SWIZZLE_8_BYTE(pSgpeHdr->g_sgpe_chtm_mem_cfg));
FAPI_INF("PGPE Flag Value : 0x%08x", SWIZZLE_2_BYTE(pPgpeHdr->g_pgpe_flags));
FAPI_DBG(" -------------------- CME/SGPE Flags Ends ---------------==");
fapi_try_exit:
return fapi2::current_err;
}
//------------------------------------------------------------------------------
/**
* @brief updates various CPMR fields which are associated with scan rings.
* @param i_pChipHomer points to start of P9 HOMER.
*/
void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer )
{
cpmrHeader_t* pCpmrHdr =
(cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader);
cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
//Updating CPMR Header using info from CME Header
pCpmrHdr->cmeImgOffset = SWIZZLE_4_BYTE((CME_IMAGE_CPMR_OFFSET >> CME_BLK_SIZE_SHIFT));
pCpmrHdr->cmePstateOffset = CME_IMAGE_CPMR_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset);
pCpmrHdr->cmePstateOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset);
pCpmrHdr->cmePstateLength = pCmeHdr->g_cme_pstate_region_length;
pCpmrHdr->cmeImgLength = pCmeHdr->g_cme_hcode_length;// already swizzled
pCpmrHdr->coreScomOffset = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_CPMR_OFFSET);
pCpmrHdr->coreScomLength = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_TOTAL);
if( pCmeHdr->g_cme_common_ring_length )
{
pCpmrHdr->cmeCommonRingOffset = CME_IMAGE_CPMR_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset);
pCpmrHdr->cmeCommonRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset);
pCpmrHdr->cmeCommonRingLength = pCmeHdr->g_cme_common_ring_length;
}
if( pCmeHdr->g_cme_max_spec_ring_length )
{
pCpmrHdr->coreSpecRingOffset = ( SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) << CME_BLK_SIZE_SHIFT ) +
SWIZZLE_4_BYTE( pCpmrHdr->cmeImgLength) +
SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength) +
SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength);
pCpmrHdr->coreSpecRingOffset = (pCpmrHdr->coreSpecRingOffset + CME_BLOCK_READ_LEN - 1) >> CME_BLK_SIZE_SHIFT;
pCpmrHdr->coreSpecRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset);
pCpmrHdr->coreSpecRingLength = pCmeHdr->g_cme_max_spec_ring_length; // already swizzled
}
//Updating CME Image header
pCmeHdr->g_cme_magic_number = SWIZZLE_8_BYTE(CME_MAGIC_NUMBER);
pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length) +
SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) +
SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length);
pCmeHdr->g_cme_scom_offset =
((pCmeHdr->g_cme_scom_offset + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT);
//Adding to it instance ring length which is already a multiple of 32B
pCmeHdr->g_cme_scom_offset += SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length);
pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset);
pCmeHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_PER_CME);
FAPI_INF("========================= CME Header Start ==================================");
char magicWord[16] = {0};
uint64_t temp = pCmeHdr->g_cme_magic_number;
memcpy(magicWord, &temp, sizeof(uint64_t));
FAPI_DBG(" Magic Num : %s", magicWord);
FAPI_INF(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset));
FAPI_INF(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length));
FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset));
FAPI_INF(" PS Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length));
FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset));
FAPI_INF(" CR Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset ));
FAPI_INF(" CR Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length));
FAPI_INF(" CSR Offset : 0x%08X (Real offset / 32) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset));
FAPI_INF(" CSR Length : 0x%08X (Real length / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) );
FAPI_INF(" SCOM Offset : 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset));
FAPI_INF(" SCOM Area Len : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length));
FAPI_INF(" CPMR Phy Add : 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr));
FAPI_INF("========================= CME Header End ==================================");
FAPI_INF("==========================CPMR Header===========================================");
temp = pCpmrHdr->magic_number;
memcpy(magicWord, &temp, sizeof(uint64_t));
FAPI_DBG(" Magic Num : %s", magicWord);
FAPI_INF(" CME HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset));
FAPI_INF(" CME HC Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength));
FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset));
FAPI_INF(" PS Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength));
FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset));
FAPI_INF(" CR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength));
FAPI_INF(" CSR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset));
FAPI_INF(" CSR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength));
FAPI_INF(" Core SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset));
FAPI_INF(" Core SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength ));
FAPI_INF("==================================CPMR Ends=====================================");
}
//------------------------------------------------------------------------------
/**
* @brief updates various CPMR fields which are associated with self restore code.
* @param i_pChipHomer points to start of P9 HOMER.
* @param i_fuseState core fuse status
*/
void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState )
{